LFE5UM5G-85F-8BG554I ApplicationField
-Wireless Technology
-Internet of Things
-Medical Equipment
-Industrial Control
-Cloud Computing
-Consumer Electronics
-5G Technology
-Artificial Intelligence
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LFE5UM5G-85F-8BG554I FAQ Chips
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ICs LFE5UM5G-85F-8BG554I Features
194K to 669K bits distributed RAM
sysDSP
Soft Error Injection – Emulate SEU event to debug system error handling
Supports eDP in RDR (1.62 Gb/s) and HDR (2.7 Gb/s)
Rounding and truncation
On-chip oscillator for initialization and general use
Time Division Multiplexing MAC Sharing
IEEE 1149.1 and IEEE 1532 compliant
12 to 160 slices for high performance multiply and accumulate
Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI
subLVDS and SLVS, SoftIP MIPI D-PHY receiver/transmitter interfaces
Programmable sysI/O Buffer Supports Wide Range of Interfaces
Higher Logic Density for Increased System Integration
sysCLOCK Analog PLLs and DLLs
Advanced 18 x 36 MAC and 18 x 18 Multiply-Multiply-Accumulate (MMAC) operations
Fully cascadable slice architecture
LVTTL and LVCMOS 33/25/18/15/12
Soft Error Detect – Embedded hard macro
ADC/DAC, 7:1 LVDS, XGMII
Each slice supports
Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate
Source synchronous standards support
Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers
Soft Error Correction – Without stopping user operation
270 Mb/s, up to 5.0 Gb/s, SERDES interface(ECP5-5G)
Slave SPI
Up to 3.744 Mb sysMEM Embedded Block RAM (EBR)
Pre-Engineered Source Synchronous I/O
Flexible Memory Resources
SPI boot flash interface
High Speed ADC/DAC devices
Shared bank for configuration I/O
System Level Support
DDR registers in I/O cells
1.1 V core power supply for ECP5, 1.2 V core power supply for ECP5UM5G
Dedicated gearing logic
Single Event Upset (SEU) Mitigation Support
SSTL 18/15 I, II
LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
Reveal Logic Analyzer
TransFR I/O for simple field updates
Embedded SERDES
HSUL12
On-chip termination
270 Mb/s, up to 3.2 Gb/s, SERDES interface(ECP5)
197 to 365 user programmable I/O
Four DLLs and four PLLs in LFE5-45 and LFE5-85; two DLLs and two PLLs in LFE5-25 and LFE5-12
Flexible Device Configuration
Dedicated read/write levelling functionality
Dual-boot images supported
Powerful 54-bit ALU operations
12K to 84K LUTs
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Xilinx LFE5UM5G-85F-8BG554I Overview
The LFE5UM5G-85F-8BG554I devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 40 nm technology making the devices suitable for high-volume, highspeed, and low-cost applications.
The LFE5UM5G-85F-8BG554I covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 user I/O. The LFE5UM5G-85F-8BG554I device family also offers up to 156 18 x 18 multipliers and a wide range of parallel I/O standards. The ECP5/ECP5-5G FPGA fabric is optimized high performance with low power and low cost in mind. The LFE5UM5G-85F-8BG554I devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distributed and embedded memory, Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities.
The pre-engineered source synchronous logic implemented in the ECP5/ECP5-5G device family supports a broad range of interface standards including DDR2/3, LPDDR2/3, XGMII, and 7:1 LVDS. The LFE5UM5G-85F-8BG554I also features high speed SERDES with dedicated Physical Coding Sublayer (PCS) functions. High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit De-emphasis with pre- and post-cursors, and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media.
The LFE5UM5G-85F-8BG554I devices also provide flexible, reliable and secure configuration options, such as dual-boot capability, bit-stream encryption, and TransFR field upgrade features. ECP5-5G family devices have made some enhancement in the SERDES compared to ECP5UM devices. These enhancements increase the performance of the SERDES to up to 5 Gb/s data rate.The LFE5UM5G-85F-8BG554I devices are pin-to-pin compatible with the ECP5UM devices. These allows a migration path for you to port designs from ECP5UM to ECP5-5G devices to get higher performance.
The Lattice Diamond design software allows large complex designs to be efficiently implemented using the ECP5/ECP5-5G FPGA family. Synthesis library support for ECP5/ECP5-5G devices is available for popular logic synthesis tools. The Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LFE5UM5G-85F-8BG554I device. The tools extract the timing from the routing and back-annotate it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) modules for the LFE5UM5G-85. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
The Lattice Embedded – FPGAs (Field Programmable Gate Array) series LFE5UM5G-85F-8BG554I is IC FPGA 259 I/O 554CABGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
LFE5UM5G-85F-8BG554I Tags integrated circuit
1. LFE5UM5G-85F-8BG554I Datasheet PDF
2. Lattice LFE5UM5G-85
3. LFE5UM5G-85 evaluation board
4. ECP5 starter kit
5. ECP5 evaluation kit
6. LFE5UM5G-85 development board
7. LFE5UM5G-85 reference design
8. ECP5 LFE5UM5G-85
9. ECP5 starter kit
Xilinx LFE5UM5G-85F-8BG554I TechnicalAttributes
-Voltage – Supply 1.045V ~ 1.155V
-Number of Logic Elements/Cells 84000
-Package / Case 554-FBGA
-Mounting Type Surface Mount
-Operating Temperature -40℃ ~ 100℃ (TJ)
-Number of LABs/CLBs 21000
-Number of I/O 259
-Supplier Device Package 554-CABGA (23×23)
-Total RAM Bits 3833856
