How to order Xilinx XC3S700A-4FG484I FPGA

The device XC3S700A-4FG484I hails from the Spartan-3A FPGA family. This family has provided solutions to design challenges in electronic applications which comes up with attributes such as superior volume, cost considerations and I/O enrichment. In short, these devices show case low cost with high end performance. XC3S700A-4FG484I devices are multi voltage and multi standard. The XC3S700A-4FG484I device exhibit more than 640 Mb per second transfer rate. All the ICs in this family are equipped with DDR, DDR2 or SDRAM which support maximum 400 Mb per second. These devices have plentiful maximum logic resources. Architectural build up of these devices comes up with hierarchical SelectRAM™. Spartan-3A FPGA family’s is a group of 5 notable devices including XC3S50A, XC3S50A, XC3S400A, XC3S700A, and XC3S1400A. Body size of 4FG484I package is 23 by 23 mm with maximum height is 2.43 mm. These devices are equipped with packaging tray type. Lead free option is also available in these devices. These devices can operate in extreme temperature conditions ranging from -40 °C to 100 °C. Spartan-3A FPGA is a very economical ICs family with effective application range in different electronic applications. The XC3S700A-4FG484I device comes up with 372 I/O with 484 number of terminations and having ball type termination.

XC3S700A-4FG484I Properties:

 XC3S700A-4FG484I devices come with Fine pitch Ball Grid Array also known as FBGA Array. These are surface mounted devices with a pin count of 484. These devices are designed for 372 user I/O and 165 differential I/O (I/O and input-only pins). The XC3S700A-4FG484I devices offer maximum I/O of 375 with 1.0 mm Lead Pitch having body height of 2.60 mm. XC3S700A family is designed with 700K system gates having 13,248 equivalent logic cells. Configurable Logic Array of this family consists of 48 rows and 32 columns with total 1,472 CLBs (one CLB is equal to 4 slices thus making 5,888 total slices). The device comes up with 72K Distributed RAM bits having 360K blocked RAM bits. These devices are equipped with 20 dedicated multipliers and equipped with Eight DCMs.

I/O Timings:

Xilinx FPGA

XC3S700A-4FG484I devices are equipped with Pins T8, U7 and U16 which are movable from left device to right device without any condition.

Clock to Output timings of XC3S700A-4FG484I devices are set between 3.39 ns to 3.50 ns with Digital Clock Manager (DCM) usage. Similarly, these devices are equipped with output timings with settings between 4.97 ns to 5.34 ns with no Digital Clock Manager usage. Digital Clock Manager jitter is included in all explained output timings.

Pin to Pin setup times for the IOB input path for XC3S700A-4FG484I devices are set between 2.38 ns to 2.57 ns with Digital Clock Manager (DCM) usage and configured Input delay. While pin to pin setup times for the same device are set between 2.28 ns to 2.63 ns with no Digital Clock Manager (DCM) usage and with programmed input delay. Hold time for XC3S700A-4FG484I devices vary between -0.17 ns to -0.12 ns when DCM is in use with no programmed input delay and Hold time vary between -0.80 ns to -0.74 ns when no DCM is in use with programmed input delay.

Clock Timing:

All XC3S700A-4FG484I devices has the frequency of TCK signal ranging from 0 MHz (minimum) to 20 MHz (maximum).

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