Xilinx FPGA

What is Xilinx XC3S700A-4FGG484C FPGA ?

One of the notable family members of Spartan-3A is XC3S700A-4FGG484C. Body size of 4FGG484C package is 23 by 23 mm with maximum height is 2.60 mm. XC3S700A-4FGG484C devices are surface mounted having 484 pins. These devices come up with packaging tray type. The devices come with lead free option as well having Moisture Sensitivity Level (MSL) up to 168 hours. The XC3S700A-4FGG484C device comes up with 372 I/O with 484 number of terminations. These devices can tolerate a wide range of temperature ranging from -40 °C to 100 °C. Spartan-3A FPGA is a very economical ICs family with effective application range in different electronic applications.

XC3S700A-4FGG484C Properties:

 XC3S700A-4FGG484C devices are equipped with Fine pitch Ball Grid Array also known as FBGA Array. These devices are made up of 4 banks having 5 GND pairs per bank. XC3S700A-4FGG484C device consists of 1,472 Configurable Logic Control array with 4 slices. The device comes up with 72K Distributed RAM bits having 360K blocked RAM bits. These devices are designed with Twenty dedicated multipliers and equipped with Eight DCMs. XC3S700A-4FGG484C devices come up with power and ground supply pins with VCCINT (15), VCCAUX (10), VCCO (24), and GND (23). These devices are designed for Quiescent current supply of 120 mA (commercial maximum) and 185 mA (industrial maximum).

I/O Timings:

XC3S700A-4FGG484C contains Pins T8, U7 and U16 which can easily move from left device to right device unconditionally. I/O distribution in these devices at top, right, bottom and left edge is 92, 94, 92 and 94 respectively with maximum I/O of 372.

Clock to Output timings of XC3S700A-4FGG484C devices are optimized from 3.39 ns to 3.50 ns with Digital Clock Manager (DCM) is in use. Similarly, these devices are optimized at output timing from 4.97 ns to 5.34 ns with no Digital Clock Manager in use. It is important to note here that Digital Clock Manager jitter is inclusive in all of the above measurements.

Pin to Pin setup times for the IOB input path for XC3S700A-4FGG484C devices ranges from 2.38 ns to 2.57 ns when the Digital Clock Manager (DCM) is in use with no configured Input delay. While pin to pin setup times for the same device ranges from 2.28 ns to 2.63 ns when no Digital Clock Manager (DCM) is in use with programmed input delay. On the other hand, Hold time for XC3S700A-4FGG484C devices ranges from -0.17 ns to -0.12 ns when DCM is in use with no programmed input delay and Hold time ranges from -0.80 ns to -0.74 ns when no DCM is in use with programmed input delay.

Clock Timing:

All XC3S700A-4FGG484C devices has the frequency of TCK signal clocked at 0 MHz (minimum) to 20 MHz (maximum).

Thermal Characteristics:

XC3S700A-4FGG484C devices exhibit thermal resistance factor ranging from 7.9 °C/Watt for Case to Junction and 12.8 °C/Watt for Junction to Board. While Junction to ambient thermal resistance clocked at 22.3 °C/Watt when air is still. The thermal resistance tends to go on lower side with increasing air flows from 250 LFM to 750 LFM.

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