Xilinx QPro FPGA

What is XILINX XC3S700A-5FGG484C FPGA

One of the important members of Spartan-3A FPGA family is XC3S700A-5FGG484C. Building Blocks of Spartan-3A FPGA are earlier developed Spartan families such as 3E and Spartan-3. Spartan-3A FPGA comes up with state of the art attributes such as wide range I/O protocols and soft processor. XC3S700A-5FGG484C device belonging to this family also provide dual benefit such as improved system efficiency with low programming cost. As explained, these devices are pocket friendly, thus these have found a vast range of usage in different applications such as electronic television, broadband technology as well as home networking setup. Spartan-3A FPGA family comes up with up to eight Digital Clock Managers having plentiful and modifiable logic resources.

XC3S700A-5FGG484C Properties:

XC3S700A-5FGG484C devices comprise of 700 thousand system gates, 13,248 equivalent logic cells. Configurable Logic Control (CLB) array of such kind of devices includes 48 rows and 32 columns.  XC3S700A-5FGG484C contains 1,472 CLBs with each CLB consisting of 4 slices thus making total slices as 5,888. Distributed RAM bits of these devices are clocked at 92,000 with Block RAM bits of 360K. XC3S700A-5FGG484C devices have 20 dedicated multipliers with eight Digital Clock Managers (DCMs) having maximum user I/O at 372 and maximum differential I/O pairs at 165. Quiescent Supply Current Characteristics of these devices are 120 mA for commercial maximum and 185 mA for Industrial maximum for Quiescent VCCINT supply current. Quiescent VCCO supply current is clocked at 3 mA & 4 mA for commercial and industrial maximum respectively. While Quiescent VCCAUX supply current for these devices is 28 mA and 34 mA for commercial and industrial maximum respectively.

I/O Timings:

Clock to Output timings of XC3S700A-5FGG484C devices ranges from 3.39 ns to 3.50 ns when Digital Clock Manager (DCM) is in use. When Digital Clock Manager (DCM) is not in use the Clock to Output timing of these devices ranges from 4.97 ns to 5.34 ns. It is worth noting that DCM output jitter is included in all above measurements.

Pin to Pin setup times for the IOB input path for XC3S700A-5FGG484C devices ranges from 2.38 ns to 2.57 ns when the Digital Clock Manager (DCM) is in use with no configured Input delay. While pin to pin setup times for the same device ranges from 2.28 ns to 2.63 ns when no Digital Clock Manager (DCM) is in use with programmed input delay. On the other hand, Hold time for XC3S700A-5FGG484C devices ranges from -0.17 ns to -0.12 ns when DCM is in use with no programmed input delay and Hold time ranges from -0.80 ns to -0.74 ns when no DCM is in use with programmed input delay.

Clock Timing:

All XC3S700A-5FGG484C devices has the frequency of TCK signal clocked at 0 MHz (minimum) to 20 MHz (maximum).

Thermal Characteristics:

XC3S700A-5FGG484C devices exhibit thermal resistance factor ranging from 7.9 °C/Watt for Case to Junction and 12.8 °C/Watt for Junction to Board. While Junction to ambient thermal resistance clocked at 22.3 °C/Watt when air is still. The thermal resistance tends to go on lower side with increasing air flows from 250 LFM to 750 LFM.

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