EP1AGX90EF1152I6 ApplicationField
-Artificial Intelligence
-5G Technology
-Medical Equipment
-Wireless Technology
-Consumer Electronics
-Internet of Things
-Cloud Computing
-Industrial Control
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ICs EP1AGX90EF1152I6 Features
■ 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers
(POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
■ High-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters
■ Support for numerous single-ended and differential I/O standards
■ TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 380 MHz
■ Support for the following CDR-based bus standards—PCI Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial-based IP using its Basic mode
■ Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation
■ High-speed source-synchronous differential I/O support on up to 47 channels
■ Support for high-speed external memory including DDR and DDR2 SDRAM, and SDR SDRAM
■ Hot socketing feature for hot plug-in or hot swap and power sequencing support without the use of external devices
■ Receiver indicator for loss of signal (available only in PCI Express [PIPE] mode)
■ Support for multiple intellectual property megafunctions from Altera MegaCore functions and Altera Megafunction Partners Program (AMPPSM)
■ Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array
■ Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial Digital Interface (SDI), and Serial RapidIO
■ Channel aligner compliant with XAUI
■ Support for remote configuration updates
■ Up to 16 global clock networks with up to 32 regional clock networks per device
■ 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
■ Support for source-synchronous bus standards, including SPI-4 Phase 2
■ Main device features:
■ Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels
■ Up to four enhanced phase-locked loops (PLLs) per device provide spread spectrum, programmable bandwidth, clock switch-over, and advanced multiplication and phase shifting
■ High-speed serial transceiver channels with CDR support up to 3.125 Gbps.
■ Transceiver block features
The key features of Arria GX devices include:
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Xilinx EP1AGX90EF1152I6 Overview
The Arria GX family of devices combines 3.125 Gbps serial transceivers with reliable packaging technology and a proven logic array. Arria GX EP1AGX90EF1152I6 devices include 4 to 12 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES circuitry designed to support PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with the ability to develop proprietary, serial-based IP using its Basic mode. The transceivers build upon the success of the Stratix II GX family. The Arria GX FPGA technology offers a 1.2-V logic array with the right level of performance and dependability needed to support these mainstream protocols.Arria GX EP1AGX90EF1152I6 devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix II GX device family.Arria GX EP1AGX90EF1152I6 transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks located on the right side of the device. The transceiver blocks can be configured to support the following serial connectivity protocols (functional modes): ■ PCI Express (PIPE)■ Gigabit Ethernet (GIGE)■ XAUI■ Basic (600 Mbps to 3.125 Gbps)■ SDI (HD, 3G)■ Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)Transceivers within each block are independent and have their own set of dividers. Therefore, each transceiver can operate at different frequencies.Each block can select from two reference clocks to provide two clock domains that each transceiver can select from.
The INTEL Programmable Logic ICs series EP1AGX90EF1152I6 is FPGA – Field Programmable Gate Array FPGA – Arria GX 4511 LABs 538 IOs, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
EP1AGX90EF1152I6 Tags integrated circuit
1. EP1AGX90EF1152I6 Datasheet PDF
2. Arria GX evaluation kit
3. Arria GX EP1AGX90E
4. INTEL Arria GX development board
5. EP1AGX90E development board
6. INTEL EP1AGX90E
7. Arria GX starter kit
8. EP1AGX90E reference design
9. INTEL Arria GX development board
Xilinx EP1AGX90EF1152I6 TechnicalAttributes
-Packaging Tray
-Maximum Operating Frequency 622.08 MHz
-Mounting Style SMD/SMT
-Number of I/Os 538
-Maximum Operating Temperature + 85℃
-Number of Logic Blocks 4511
-Operating Supply Voltage 1.2 V to 3.3 V
-Series Arria GX
-Operating Supply Current 0.62 A
-Minimum Operating Temperature – 40℃
-Package / Case FBGA-1152
-Distributed RAM 4.4 Mbit
