EP1C12F324I7N ApplicationField
-Cloud Computing
-Consumer Electronics
-Medical Equipment
-5G Technology
-Internet of Things
-Wireless Technology
-Industrial Control
-Artificial Intelligence
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ICs EP1C12F324I7N Features
The Cyclone device family offers the following features:
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Xilinx EP1C12F324I7N Overview
Features
■ 2,910 to 20,060 LEs, see Table 1
■ Up to 294,912 RAM bits (36,864 bytes)
■ Supports configuration through low-cost serial configuration device
■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
■ Support for 66-MHz, 32-bit PCI standard
■ Low speed (311 Mbps) LVDS I/O support
■ Up to two PLLs per device provide clock multiplication and phase
shifting
■ Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
■ Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
■ Support for multiple intellectual property (IP) cores, including
Altera
MegaCore
functions and Altera Megafunctions Partners
Program (AMPPSM) megafunctions
Functional
Description
Cyclone devices contain a two-dimensional row- and column-based
architecture to implement custom logic. Column and row interconnects of
varying speeds provide signal interconnects between LABs and
embedded memory blocks.
The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small
unit of logic providing efficient implementation of user logic functions.
LABs are grouped into rows and columns across the device. Cyclone
devices range between 2,910 to 20,060 LEs.
M4K RAM blocks are true dual-port memory blocks with 4K bits of
memory plus parity (4,608 bits). These blocks provide dedicated true
dual-port, simple dual-port, or single-port memory up to 36-bits wide at
up to 200 MHz. These blocks are grouped into columns across the device
in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of
embedded RAM.
Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the
ends of LAB rows and columns around the periphery of the device. I/O
pins support various single-ended and differential I/O standards, such as
the 66-MHz, 32-bit PCI standard and the LVDS I/O standard at up to
311 Mbps. Each IOE contains a bidirectional I/O buffer and three registers
for registering input, output, and output-enable signals. Dual-purpose
DQS, DQ, and DM pins along with delay chains (used to phase-align DDR
signals) provide interface support with external memory devices such as
DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps).
Cyclone devices provide a global clock network and up to two PLLs. The
global clock network consists of eight global clock lines that drive
throughout the entire device. The global clock network can provide clocks
for all resources within the device, such as IOEs, LEs, and memory blocks.
The global clock lines can also be used for control signals. Cyclone PLLs
provide general-purpose clocking with clock multiplication and phase
shifting as well as external outputs for high-speed differential I/O
support.
Figure 1 shows a diagram of the Cyclone EP1C12F324I7N device
The INTEL Embedded – FPGAs (Field Programmable Gate Array) series EP1C12F324I7N is Cyclone FPGA 12K FBGA-324, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
EP1C12F324I7N Tags integrated circuit
1. INTEL EP1C12
2. Cyclone FPGA evaluation kit
3. EP1C12 development board
4. EP1C12 reference design
5. INTEL Cyclone FPGA development board
6. EP1C12F324I7N Datasheet PDF
7. Cyclone FPGA starter kit
8. EP1C12 evaluation board
9. EP1C12 reference design
Xilinx EP1C12F324I7N TechnicalAttributes
-Embedded Block RAM – EBR 4 Kbit
-Series Cyclone
-Operating Supply Voltage 1.5 V to 3.3 V
-Mounting Style SMD/SMT
-Number of Logic Blocks 1206
-Distributed RAM 239 kbit
-Minimum Operating Temperature – 40℃
-Maximum Operating Temperature + 85℃
-Package / Case FBGA-324
-Packaging Tray
-Number of I/Os 249
-Maximum Operating Frequency 250 MHz
