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EP1M350F780C6N FAQ Chips
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ICs EP1M350F780C6N Features
– Dedicated multiplier circuitry for high-speed implementation of signed or unsigned multiplication up to 16 × 16
– Up to four general-purpose phase-locked loops (PLLs) with programmable multiplication and delay shifting
– Up to 12 PLL output ports
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Xilinx EP1M350F780C6N Overview
Mercury EP1M350F780C6N devices integrate high-speed differential transceivers and support for CDR with a speed-optimized PLD architecture. These transceivers are implemented through the dedicated serializer, deserializer, and clock recovery circuitry in the HSDI and incorporate support for the LVDS, LVPECL, and 3.3-V PCML I/O standards. This circuitry, together with enhanced I/O elements (IOEs) and support for numerous I/O standards, allows Mercury devices to meet high-speed interface requirements.Mercury EP1M350F780C6N are the first PLDs optimized for core performance. These LUT-based, enhanced memory devices use a network of fast routing resources to achieve optimal performance. These resources are ideal for data-path, register-intensive, mathematical, digital signal processing (DSP), or communications designs.
EP1M350F780C6N Tags integrated circuit
1. EP1M350 reference design
2. Altera EP1M350
3. Altera Mercury PLD development board
4. EP1M350 evaluation board
5. Mercury PLD EP1M350
6. EP1M350F780C6N Datasheet PDF
7. Mercury PLD evaluation kit
8. Mercury PLD starter kit
9. EP1M350 evaluation board
Xilinx EP1M350F780C6N TechnicalAttributes
-Package / Case FBGA-780
-Minimum Operating Temperature – 40 C
-Distributed RAM 114 kbit
-Operating Supply Voltage 3.3 V
-Mounting Style SMD/SMT
-Maximum Operating Temperature + 85 C
-Number of I/Os 486
-Operating Supply Current 50 mA
-Number of Logic Blocks 1440