EP1M350F780I5 ApplicationField
-Cloud Computing
-Internet of Things
-Artificial Intelligence
-Consumer Electronics
-5G Technology
-Industrial Control
-Medical Equipment
-Wireless Technology
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EP1M350F780I5 FAQ Chips
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ICs EP1M350F780I5 Features
– Up to four general-purpose phase-locked loops (PLLs) with programmable multiplication and delay shifting
– Dedicated multiplier circuitry for high-speed implementation of signed or unsigned multiplication up to 16 × 16
System-level features
– Up to 12 PLL output ports
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Xilinx EP1M350F780I5 Overview
Mercury EP1M350F780I5 devices integrate high-speed differential transceivers and support for CDR with a speed-optimized PLD architecture. These transceivers are implemented through the dedicated serializer, deserializer, and clock recovery circuitry in the HSDI and incorporate support for the LVDS, LVPECL, and 3.3-V PCML I/O standards. This circuitry, together with enhanced I/O elements (IOEs) and support for numerous I/O standards, allows Mercury devices to meet high-speed interface requirements.Mercury EP1M350F780I5 are the first PLDs optimized for core performance. These LUT-based, enhanced memory devices use a network of fast routing resources to achieve optimal performance. These resources are ideal for data-path, register-intensive, mathematical, digital signal processing (DSP), or communications designs.
EP1M350F780I5 Tags integrated circuit
1. EP1M350F780I5 Datasheet PDF
2. Altera EP1M350
3. EP1M350 reference design
4. Mercury PLD evaluation kit
5. Mercury PLD starter kit
6. EP1M350 development board
7. Altera Mercury PLD development board
8. EP1M350 evaluation board
9. Mercury PLD evaluation kit
Xilinx EP1M350F780I5 TechnicalAttributes
-Operating Supply Voltage 3.3 V
-Maximum Operating Temperature + 85 C
-Series Mercury
-Mounting Style SMD/SMT
-Packaging Tray
-Operating Supply Current 50 mA
-Number of Logic Blocks 1440
-Number of I/Os 486
-Minimum Operating Temperature – 40 C
-Package / Case FBGA-780
-Distributed RAM 114 kbit