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EP1SGX40GF1020C5ES FAQ Chips
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ICs EP1SGX40GF1020C5ES Features
■ Supports flexible reference clock generation capabilities, including a dedicated transmitter phase-locked loop (PLL) and four receiver PLLs per gigabit transceiver block
■ Includes built-in self test (BIST) capability, including embedded Pseudo Random Binary Sequence (PRBS) pattern generation and verification
■ Implements XAUI physical media attachment (PMA) and physical coding sublayer (PCS) functionality for 10GBASE-X systems
■ Includes three independent loopback paths for system verification
■ Supports programmable pre-emphasis, equalization, and programmable VOD settings in I/O buffers, and dynamic reprogrammability for each of these features
■ Integrates serializer/deserializer (SERDES), clock data recovery (CDR), word aligner, channel aligner, rate matcher, 8B/10B encoder/decoder, byte serializer/deserializer, and phase compensation first-in first-out (FIFO) modules
■ Provides individual transmitter and receiver power-down capability for reduced power consumption during non-operation
■ Supports frequencies from 500 megabits per second (Mbps) to 3.1875 Gbps
■ Provides built-in Gigabit Ethernet (GigE) physical coding sublayer functionality
Each self-contained Stratix GX gigabit transceiver
block supports a variety of embedded functions and does the following:
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Xilinx EP1SGX40GF1020C5ES Overview
Stratix EP1SGX40GF1020C5ES devices combine highly advanced 3.1875-gigabit-per-second (Gbps) four-channel gigabit transceiver blocks with one of the industry’s most advanced FPGA architectures. Stratix GX devices are manufactured on a 1.5-V, 0.13-µm, all-layer copper CMOS process technology with 1.5- V PCML I/O standard support.Historically, designers have used high-speed transceivers in strictly structured, line-side applications. Now, with the new gigabit transceiver blocks embedded in FPGAs, you can use transceivers in a host of new systems that require flexibility, increased time-to-market, high performance, and top-of-the-line features.Stratix GX EP1SGX40GF1020C5ES devices are organized into four-channel blocks with four 3.1875 Gbps full-duplex channels per block and up to 20 channels (in five blocks) per device.
EP1SGX40GF1020C5ES Tags integrated circuit
1. EP1SGX40 reference design
2. Stratix GX evaluation kit
3. Stratix GX starter kit
4. EP1SGX40 development board
5. EP1SGX40GF1020C5ES Datasheet PDF
6. Stratix GX EP1SGX40
7. Altera EP1SGX40
8. EP1SGX40 evaluation board
9. EP1SGX40 development board
Xilinx EP1SGX40GF1020C5ES TechnicalAttributes
-Number of Logic Blocks 4125
-Minimum Operating Temperature 0 C
-Distributed RAM 3.4 Mbit
-Maximum Operating Frequency 684 MHz
-Series Stratix GX
-Maximum Operating Temperature + 70 C
-Number of I/Os 624
-Operating Supply Voltage 1.5 V to 3.3 V
-Mounting Style SMD/SMT
-Package / Case FBGA-1020