EP2S60F672I4 -Internet of Things -5G Technology

EP2S60F672I4 ApplicationField

-Wireless Technology
-Industrial Control
-Artificial Intelligence
-Medical Equipment
-Consumer Electronics
-5G Technology
-Cloud Computing
-Internet of Things

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EP2S60F672I4 FAQ Chips 

Q: Does the price of EP2S60F672I4 devices fluctuate frequently?
A: The RAYPCB search engine monitors the EP2S60F672I4 inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.

Q: How to obtain EP2S60F672I4 technical support documents?
A: Enter the “EP2S60F672I4” keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .

Q: Where can I purchase INTEL EP2S60 Development Boards, Evaluation Boards, or Stratix II FPGA Starter Kit? also provide technical information?
A: RAYPCB does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.

Q: How can I obtain software development tools related to the INTEL FPGA platform?
A: Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.

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A: No, only submit the quantity, email address and other contact information required for the inquiry of EP2S60F672I4, but you need to sign up for the post comments and resource downloads.

Q: What should I do if I did not receive the technical support for EP2S60F672I4 in time?
A: Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the EP2S60F672I4 pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

ICs EP2S60F672I4 Features

The Stratix II family offers the following features:

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Xilinx EP2S60F672I4 Overview

Following the immensely successful first-generation Cyclone® device
family, Altera® Cyclone II FPGAs extend the low-cost FPGA density
range to 68,416 logic elements (LEs) and provide up to 622 usable I/O
pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are
manufactured on 300-mm wafers using TSMC’s 90-nm low-k dielectric
process to ensure rapid availability and low cost. By minimizing silicon
area, Cyclone II devices can support complex digital systems on a single
chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who
compromise power consumption and performance for low-cost, Altera’s
latest generation of low-cost FPGAs—Cyclone II FPGAs, offer 60% higher
performance and half the power consumption of competing 90-nm
FPGAs. The low cost and optimized feature set of Cyclone II FPGAs make
them ideal solutions for a wide array of automotive, consumer,
communications, video processing, test and measurement, and other
end-market solutions. Reference designs, system diagrams, and IP, found
at www.altera.com, are available to help you rapidly develop complete
end-market solutions using Cyclone II FPGAs.


■ High-density architecture with 4,608 to 68,416 LEs 

● M4K embedded memory blocks 

● Up to 1.1 Mbits of RAM available without reducing available

● 4,096 memory bits per block (4,608 bits per block including 512
parity bits) 

● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,
and ×36 

● True dual-port (one read and one write, two reads, or two
writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes 

● Byte enables for data input masking during writes 

● Up to 260-MHz operation 

■ Embedded multipliers 

● Up to 150 18- × 18-bit multipliers are each configurable as two
independent 9- × 9-bit multipliers with up to 250-MHz

● Optional input and output registers 

■ Advanced I/O support 

● High-speed differential I/O standard support, including LVDS,
RSDS, mini-LVDS, LVPECL, differential HSTL, and differential

● Single-ended I/O standard support, including 2.5-V and 1.8-V,
SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI
and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-,
and 1.8-V LVTTL 

● Peripheral Component Interconnect Special Interest Group (PCI
SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V
operation at 33 or 66 MHz for 32- or 64-bit interfaces 

● PCI Express with an external TI PHY and an Altera PCI Express
×1 Megacore® function

● 133-MHz PCI-X 1.0 specification compatibility 

● High-speed external memory support, including DDR, DDR2,
and SDR SDRAM, and QDRII SRAM supported by drop in
Altera IP MegaCore functions for ease of use 

● Three dedicated registers per I/O element (IOE): one input
register, one output register, and one output-enable register 

● Programmable bus-hold feature 

● Programmable output drive strength feature 

● Programmable delays from the pin to the IOE or logic array 

● I/O bank grouping for unique VCCIO and/or VREF bank

● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and

● Hot-socketing operation support 

● Tri-state with weak pull-up on I/O pins before and during

● Programmable open-drain outputs 

● Series on-chip termination support 

■ Flexible clock management circuitry 

● Hierarchical clock network for up to 402.5-MHz performance 

● Up to four PLLs per device provide clock multiplication and
division, phase shifting, programmable duty cycle, and external
clock outputs, allowing system-level clock management and
skew control 

● Up to 16 global clock lines in the global clock network that drive
throughout the entire device 

■ Device configuration 

● Fast serial configuration allows configuration times less than
100 ms 

● Decompression feature allows for smaller programming file
storage and faster configuration times 

● Supports multiple configuration modes: active serial, passive
serial, and JTAG-based configuration 

● Supports configuration through low-cost serial configuration

● Device configuration supports multiple voltages (either 3.3, 2.5,
or 1.8 V) 

■ Intellectual property 

● Altera megafunction and Altera MegaCore function support,
and Altera Megafunctions Partners Program (AMPPSM)
megafunction support, for a wide range of embedded
processors, on-chip and off-chip interfaces, peripheral
functions, DSP functions, and communications functions and protocols. Visit the Altera IPMegaStore at www.altera.com to
download IP MegaCore functions. 

● Nios II Embedded Processor support

The INTEL Embedded – FPGAs (Field Programmable Gate Array) series EP2S60F672I4 is FPGA Stratix II Family 60440 Cells 711.24MHz 90nm (CMOS) Technology 1.2V 672Pin FC-FBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.

EP2S60F672I4 Tags integrated circuit

1. EP2S60 reference design
2. EP2S60 evaluation board
3. INTEL Stratix II FPGA development board
4. Stratix II FPGA EP2S60
5. Stratix II FPGA evaluation kit
6. Stratix II FPGA starter kit
7. EP2S60F672I4 Datasheet PDF
8. EP2S60 development board
9. Stratix II FPGA EP2S60

Xilinx EP2S60F672I4 TechnicalAttributes

-Series Stratix II
-Operating Supply Current 0.5 A
-Number of I/Os 492
-Mounting Style SMD/SMT
-Operating Supply Voltage 1.2 V to 3.3 V
-Package / Case FBGA-672
-Number of Logic Blocks 3022
-Distributed RAM 2.5 Mbit
-Maximum Operating Temperature + 85℃
-Minimum Operating Temperature – 40℃

-Packaging Tray

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