EPM9560ARC304-10F ApplicationField
-Industrial Control
-Medical Equipment
-5G Technology
-Artificial Intelligence
-Internet of Things
-Consumer Electronics
-Cloud Computing
-Wireless Technology
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EPM9560ARC304-10F FAQ Chips
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Q: Where can I purchase Altera EPM9560A Development Boards, Evaluation Boards, or MAX 9000 EPLD Starter Kit? also provide technical information?
A: RAYPCB does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
ICs EPM9560ARC304-10F Features
■ Fully compliant with the peripheral component interconnect Special
■ Configurable expander product-term distribution allowing up to 32
■ High-density erasable programmable logic device (EPLD) family
■ MultiVolt I/O interface operation, allowing devices to interface with
devices (PLDs) built on third-generation Multiple Array MatriX
■ Input/output registers with clear and clock enable on all I/O pins
reduction in each macrocell
■ Programmable output slew-rate control to reduce switching noise
■ 10-ns pin-to-pin logic delays with counter frequencies of up to
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std.
■ High-performance CMOS EEPROM-based programmable logic
■ FastTrack Interconnect for fast, predictable interconnect delays
product terms per macrocell
144 MHz
registered logic
(MAX) architecture
3.3-V and 5.0-V devices
■ Programmable power-saving mode for more than 50% power
Std. 1149.1-1990
■ Dual-output macrocell for independent use of combinatorial and
Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
ranging from 6,000 to 12,000 usable gates (see Table 1)
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
1149.1 Joint Test Action Group (JTAG) interface
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Xilinx EPM9560ARC304-10F Overview
The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX EPM9560ARC304-10F provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.
EPM9560ARC304-10F Tags integrated circuit
1. Altera EPM9560A
2. EPM9560A evaluation board
3. EPM9560ARC304-10F Datasheet PDF
4. EPM9560A development board
5. MAX 9000 Devices EPM9560A
6. MAX 9000 Devices starter kit
7. EPM9560A reference design
8. MAX 9000 Devices evaluation kit
9. EPM9560A development board
Xilinx EPM9560ARC304-10F TechnicalAttributes
-Maximum Operating Temperature + 85 C
-Supply Voltage – Max 5.25 V
-Supply Current 174 mA
-Minimum Operating Temperature – 40 C
-Memory Type EEPROM
-Operating Supply Voltage 5 V
-Mounting Style SMD/SMT
-Supply Voltage – Min 4.75 V
-Delay Time 10 ns
-Packaging Tray
-Maximum Operating Frequency 144 MHz
-Number of Programmable I/Os 191
-Series MAX 9000
-Package / Case QFP-240
-Number of Macrocells 560
