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GAL26CV12B-20LP FAQ Chips
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ICs GAL26CV12B-20LP Features
• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
— 90 mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocells
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Request GAL26CV12B-20LP FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx GAL26CV12B-20LP Overview
The GAL26CV12, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance 28-pin PLD available on the market. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. Expanding upon the industry standard 22V10 architecture, the GAL26CV12B-20LP eliminates the learning curve typically associated with using a new device architecture. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL26CV12B-20LP OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 devices.Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. The Lattice SPLD - Simple Programmable Logic Devices series GAL26CV12B-20LP is SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com, and you can also search for other FPGAs products. GAL26CV12B-20LP Tags integrated circuit
1. GAL26CV12B-20LP Datasheet PDF
2. GAL26CV12 development board
3. GAL26CV12 evaluation board
4. GAL26CV12 reference design
5. SPLD GAL evaluation kit
6. SPLD GAL GAL26CV12
7. SPLD GAL starter kit
8. Lattice GAL26CV12
9. GAL26CV12 reference design
Xilinx GAL26CV12B-20LP TechnicalAttributes
-Operating Temperature 0 C to + 75 C
-Supply Voltage – Max 5.25 V
-Package / Case PDIP-28
-Operating Supply Voltage 4.75 V to 5.25 V
-Delay Time 20 ns
-Logic Family GAL
-Factory Pack Quantity 13
-Maximum Operating Temperature + 75 C
-Supply Current 130 mA
-Mounting Style Through Hole
-Maximum Operating Frequency 62.5 MHz
-Number of Macrocells 12
-Supply Voltage – Min 4.75 V
-Minimum Operating Temperature 0 C