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ISPLSI1048C-50LG FAQ Chips
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ICs ISPLSI1048C-50LG Features
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Xilinx ISPLSI1048C-50LG Overview
The ispLSI 1048C/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, two Global Output Enables (GOE), four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048C/883 features 5-Volt in system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, and the interconnect to provide truly reconfigurable systems. Compared to the ispLSI 1048, the ispLSI 1048C/883 offers two additional dedicated inputs and two new Global Output Enable pins.
The basic unit of logic on the ispLSI 1048C/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 in ISPLSI1048C-50LG Diagram. There are a total of 48 GLBs in the ispLSI 1048C/883 devices. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
ISPLSI1048C-50LG Tags integrated circuit
1. ISPLSI1048C evaluation board
2. ISPLSI1048C development board
3. ISPLSI1048C reference design
4. CPLD ispLSI 1000 evaluation kit
5. Lattice ISPLSI1048C
6. CPLD ispLSI 1000 starter kit
7. Lattice CPLD ispLSI 1000 development board
8. ISPLSI1048C-50LG Datasheet PDF
9. CPLD ispLSI 1000 evaluation kit
Xilinx ISPLSI1048C-50LG TechnicalAttributes