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ISPLSI3192-70LMN FAQ Chips
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ICs ISPLSI3192-70LMN Features
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Xilinx ISPLSI3192-70LMN Overview
The ispLSI 3192 is a High Density Programmable Logic Device containing 384 Registers, 192 Universal I/O pins, five Dedicated Clock Input Pins, twelve Output Routing Pools (ORP), and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3192 features 5-Volt in-system programmability and in-system diagnostic capabilities. The ispLSI 3192 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 3192 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1…F3. There are a total of 24 of these Twin GLBs in the ispLSI 3192 device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays, and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP.
ISPLSI3192-70LMN Tags integrated circuit
1. ISPLSI3192 evaluation board
2. ISPLSI3192 reference design
3. CPLD ispLSI 3000 ISPLSI3192
4. CPLD ispLSI 3000 starter kit
5. ISPLSI3192 development board
6. Lattice ISPLSI3192
7. ISPLSI3192-70LMN Datasheet PDF
8. Lattice CPLD ispLSI 3000 development board
9. CPLD ispLSI 3000 starter kit
Xilinx ISPLSI3192-70LMN TechnicalAttributes