ISPPAC-CLK5308S-01TN48C ApplicationField
-Artificial Intelligence
-5G Technology
-Wireless Technology
-Consumer Electronics
-Industrial Control
-Internet of Things
-Cloud Computing
-Medical Equipment
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ISPPAC-CLK5308S-01TN48C FAQ Chips
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ICs ISPPAC-CLK5308S-01TN48C Features
• Zero delay buffer
■ Up to 20 Programmable Fan-out Buffers
• Programmable lock detect
– LVTTL, LVCMOS, SSTL, HSTL
• Programmable output impedance
• Programmable slew rate
– LVTTL, LVCMOS, HSTL, eHSTL, SSTL
– LVTTL, LVCMOS, SSTL, HSTL, LVDS,
• Up to +/- 5ns skew range
■ Flexible Clock Reference and External Feedback Inputs
• Up to 10 banks with individual VCCO and GND
• Programmable Feedback Standards
• Non-zero delay buffer with output divider
• Internal/external feedback
■ Four Operating Configurations
■ Up to Three Clock Frequency Domains
• Zero delay and non-zero delay buffer
• Programmable single-ended or differential input reference standards
■ Fully Integrated High-Performance PLL
• Programmable on-chip loop filter
• Programmable termination
– 1.5V, 1.8V, 2.5V, 3.3V
• Dual non-zero delay buffer
(Skew) Per Output
■ Low Output to Output Skew (<100ps)
• Coarse and fine adjustment modes
■ Exceptional Power Supply Noise Immunity
• 8 settings; minimum step size 156ps
■ All Inputs and Outputs are Hot Socket Compliant
LVPECL, Differential HSTL, Differential SSTL
■ 48-pin and 64-pin TQFP Packages
– Locked to VCO frequency
• Compatible with spread spectrum clocks
■ 8MHz to 267MHz Input/Output Operation
• Programmable single-ended output standards and individual enable controls
• Three “Power of 2” output dividers (5-bit)
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
■ Low Jitter Peak-to-Peak (< 70 ps)
– 40 to 70Ω in 5Ω increments
• Clock A/B selection multiplexer
■ Precision Programmable Phase Adjustment
■ Full JTAG Boundary Scan Test In-System Programming Support
Request ISPPAC-CLK5308S-01TN48C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx ISPPAC-CLK5308S-01TN48C Overview
ISPPAC-CLK5308S-01TN48C Lattice Semiconductor Corporation, IC BUFFER FANOUT 8OUTPUT 48TQFP
Zero Delay Buffer 8-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48-Pin TQFP TrayClock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End
The Lattice Clock & Timer ICs series ISPPAC-CLK5308S-01TN48C is Zero Delay Programmable PLL Clock Generator Single 160MHz to 400MHz 48Pin TQFP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
ISPPAC-CLK5308S-01TN48C Tags integrated circuit
1. ISPPAC-CLK5308S-01TN48C Datasheet PDF
2. ispPAC-CLK5308S evaluation board
3. Lattice ispClock 5300S development board
4. ispClock 5300S ispPAC-CLK5308S
5. ispPAC-CLK5308S development board
6. ispClock 5300S starter kit
7. ispPAC-CLK5308S reference design
8. ispClock 5300S evaluation kit
9. ispClock 5300S ispPAC-CLK5308S
Xilinx ISPPAC-CLK5308S-01TN48C TechnicalAttributes
-Supply Voltage – Max 3.6 V
-Supply Voltage – Min 3 V
-Package / Case TQFP-48
-Multiply / Divide Factor 2:8
-Packaging Tray
-Factory Pack Quantity 1250
-Output Type EHSTL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL
-Mounting Style SMD/SMT
-Maximum Power Dissipation 888 mW
-Type Zero Delay Programmable PLL Clock Generator
-Input Type HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL
-Max Output Freq 267 MHz
-Maximum Operating Temperature + 70 C
-Minimum Operating Temperature 0 C
-Supply Current 1.5 mA
