ISPPAC-CLK5312S-01T48C ApplicationField
-Wireless Technology
-Industrial Control
-Artificial Intelligence
-Internet of Things
-5G Technology
-Medical Equipment
-Cloud Computing
-Consumer Electronics
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ISPPAC-CLK5312S-01T48C FAQ Chips
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ICs ISPPAC-CLK5312S-01T48C Features
• Programmable output impedance
• Programmable on-chip loop filter
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
• Three “Power of 2” output dividers (5-bit)
• Programmable termination
• Up to +/- 5ns skew range
■ 48-pin and 64-pin TQFP Packages
■ Up to Three Clock Frequency Domains
■ Four Operating Configurations
■ 8MHz to 267MHz Input/Output Operation
• Internal/external feedback
• Programmable single-ended output standards and individual enable controls
■ Flexible Clock Reference and External Feedback Inputs
■ Low Output to Output Skew (<100ps)
■ Up to 20 Programmable Fan-out Buffers
– LVTTL, LVCMOS, HSTL, eHSTL, SSTL
■ Fully Integrated High-Performance PLL
■ Low Jitter Peak-to-Peak (< 70 ps)
(Skew) Per Output
• Zero delay and non-zero delay buffer
– 1.5V, 1.8V, 2.5V, 3.3V
■ Precision Programmable Phase Adjustment
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND
– LVTTL, LVCMOS, SSTL, HSTL
■ All Inputs and Outputs are Hot Socket Compliant
• Coarse and fine adjustment modes
LVPECL, Differential HSTL, Differential SSTL
■ Exceptional Power Supply Noise Immunity
• 8 settings; minimum step size 156ps
• Non-zero delay buffer with output divider
– 40 to 70Ω in 5Ω increments
• Programmable single-ended or differential input reference standards
• Dual non-zero delay buffer
– LVTTL, LVCMOS, SSTL, HSTL, LVDS,
• Clock A/B selection multiplexer
• Programmable lock detect
■ Full JTAG Boundary Scan Test In-System Programming Support
• Programmable Feedback Standards
– Locked to VCO frequency
• Compatible with spread spectrum clocks
• Zero delay buffer
Request ISPPAC-CLK5312S-01T48C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx ISPPAC-CLK5312S-01T48C Overview
ISPPAC-CLK5312S-01T48C Lattice Semiconductor Corporation, IC BUFFER FANOUT ISP UNIV 48TQFP
Zero Delay Buffer 12-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48-Pin TQFP Tray
The Lattice Clock & Timer ICs series ISPPAC-CLK5312S-01T48C is Zero Delay Buffer 12Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48Pin TQFP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
ISPPAC-CLK5312S-01T48C Tags integrated circuit
1. ISPPAC-CLK5312S-01T48C Datasheet PDF
2. ispPAC-CLK5312S reference design
3. ispClock 5300S ispPAC-CLK5312S
4. Lattice ispClock 5300S development board
5. Lattice ispPAC-CLK5312S
6. ispPAC-CLK5312S evaluation board
7. ispPAC-CLK5312S development board
8. ispClock 5300S evaluation kit
9. Lattice ispClock 5300S development board
Xilinx ISPPAC-CLK5312S-01T48C TechnicalAttributes
-Factory Pack Quantity 1250
-Package / Case TQFP-48
-Minimum Operating Temperature 0 C
-Maximum Operating Temperature + 70 C
-Packaging Tray
-Mounting Style SMD/SMT
