ISPPAC-CLK5312S-01T48I ApplicationField
-Wireless Technology
-Internet of Things
-5G Technology
-Consumer Electronics
-Artificial Intelligence
-Medical Equipment
-Cloud Computing
-Industrial Control
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ISPPAC-CLK5312S-01T48I FAQ Chips
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ICs ISPPAC-CLK5312S-01T48I Features
■ Up to 20 Programmable Fan-out Buffers
• Up to +/- 5ns skew range
• Three “Power of 2” output dividers (5-bit)
■ 48-pin and 64-pin TQFP Packages
■ All Inputs and Outputs are Hot Socket Compliant
• Zero delay and non-zero delay buffer
– 40 to 70Ω in 5Ω increments
■ Flexible Clock Reference and External Feedback Inputs
■ Low Output to Output Skew (<100ps)
■ 8MHz to 267MHz Input/Output Operation
• Non-zero delay buffer with output divider
• 8 settings; minimum step size 156ps
■ Full JTAG Boundary Scan Test In-System Programming Support
– LVTTL, LVCMOS, SSTL, HSTL
– LVTTL, LVCMOS, HSTL, eHSTL, SSTL
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
• Programmable output impedance
(Skew) Per Output
• Clock A/B selection multiplexer
• Programmable single-ended output standards and individual enable controls
■ Low Jitter Peak-to-Peak (< 70 ps)
• Coarse and fine adjustment modes
■ Precision Programmable Phase Adjustment
■ Fully Integrated High-Performance PLL
• Programmable slew rate
• Programmable single-ended or differential input reference standards
• Internal/external feedback
■ Up to Three Clock Frequency Domains
• Zero delay buffer
• Programmable Feedback Standards
• Programmable lock detect
• Programmable on-chip loop filter
• Programmable termination
LVPECL, Differential HSTL, Differential SSTL
– LVTTL, LVCMOS, SSTL, HSTL, LVDS,
• Compatible with spread spectrum clocks
– 1.5V, 1.8V, 2.5V, 3.3V
• Dual non-zero delay buffer
■ Four Operating Configurations
■ Exceptional Power Supply Noise Immunity
• Up to 10 banks with individual VCCO and GND
– Locked to VCO frequency
Request ISPPAC-CLK5312S-01T48I FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx ISPPAC-CLK5312S-01T48I Overview
ISPPAC-CLK5312S-01T48I Lattice Semiconductor Corporation, IC BUFFER FANOUT ISP UNIV 48TQFP
Zero Delay Buffer 12-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48-Pin TQFP Tray
The Lattice Clock & Timer ICs series ISPPAC-CLK5312S-01T48I is Zero Delay Buffer 12Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48Pin TQFP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
ISPPAC-CLK5312S-01T48I Tags integrated circuit
1. ISPPAC-CLK5312S-01T48I Datasheet PDF
2. Lattice ispClock 5300S development board
3. ispClock 5300S ispPAC-CLK5312S
4. ispPAC-CLK5312S evaluation board
5. ispClock 5300S evaluation kit
6. ispPAC-CLK5312S reference design
7. ispPAC-CLK5312S development board
8. Lattice ispPAC-CLK5312S
9. ispPAC-CLK5312S evaluation board
Xilinx ISPPAC-CLK5312S-01T48I TechnicalAttributes
-Factory Pack Quantity 1250
-Supply Voltage – Max 3.6 V
-Type Zero Delay Programmable PLL Clock Generator
-Mounting Style SMD/SMT
-Maximum Operating Temperature + 85℃
-Packaging Tray
-Supply Voltage – Min 3 V
-Minimum Operating Temperature – 40℃
-Package / Case TQFP-48
