ISPPAC-CLK5312S-01TN48C ApplicationField
-Industrial Control
-Medical Equipment
-Wireless Technology
-Cloud Computing
-5G Technology
-Artificial Intelligence
-Consumer Electronics
-Internet of Things
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ICs ISPPAC-CLK5312S-01TN48C Features
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
• Programmable lock detect
LVPECL, Differential HSTL, Differential SSTL
■ Full JTAG Boundary Scan Test In-System Programming Support
• Clock A/B selection multiplexer
(Skew) Per Output
– LVTTL, LVCMOS, SSTL, HSTL, LVDS,
– Locked to VCO frequency
• Internal/external feedback
• Programmable on-chip loop filter
• Three “Power of 2” output dividers (5-bit)
– LVTTL, LVCMOS, HSTL, eHSTL, SSTL
• Compatible with spread spectrum clocks
■ Flexible Clock Reference and External Feedback Inputs
– 1.5V, 1.8V, 2.5V, 3.3V
• Non-zero delay buffer with output divider
■ All Inputs and Outputs are Hot Socket Compliant
■ Four Operating Configurations
• Coarse and fine adjustment modes
■ 48-pin and 64-pin TQFP Packages
• Up to 10 banks with individual VCCO and GND
• 8 settings; minimum step size 156ps
■ Up to Three Clock Frequency Domains
• Programmable output impedance
• Zero delay and non-zero delay buffer
• Dual non-zero delay buffer
• Zero delay buffer
– LVTTL, LVCMOS, SSTL, HSTL
■ Low Output to Output Skew (<100ps)
■ Exceptional Power Supply Noise Immunity
• Programmable single-ended output standards and individual enable controls
■ Fully Integrated High-Performance PLL
• Programmable single-ended or differential input reference standards
– 40 to 70Ω in 5Ω increments
• Programmable slew rate
■ Low Jitter Peak-to-Peak (< 70 ps)
■ Up to 20 Programmable Fan-out Buffers
■ 8MHz to 267MHz Input/Output Operation
• Programmable termination
• Programmable Feedback Standards
■ Precision Programmable Phase Adjustment
• Up to +/- 5ns skew range
Request ISPPAC-CLK5312S-01TN48C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx ISPPAC-CLK5312S-01TN48C Overview
ISPPAC-CLK5312S-01TN48C Lattice Semiconductor Corporation, IC CLOCK PROGRAM BUFFER 48TQFP
Zero Delay Buffer 12-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48-Pin TQFP TrayClock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End
The Lattice Clock Drivers & Distribution series ISPPAC-CLK5312S-01TN48C is Zero Delay Programmable PLL Clock Generator Single 160MHz to 400MHz 48Pin TQFP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
ISPPAC-CLK5312S-01TN48C Tags integrated circuit
1. Lattice ispClock 5300S development board
2. ispClock 5300S ispPAC-CLK5312S
3. ispPAC-CLK5312S evaluation board
4. Lattice ispPAC-CLK5312S
5. ispPAC-CLK5312S development board
6. ispPAC-CLK5312S reference design
7. ISPPAC-CLK5312S-01TN48C Datasheet PDF
8. ispClock 5300S evaluation kit
9. Lattice ispPAC-CLK5312S
Xilinx ISPPAC-CLK5312S-01TN48C TechnicalAttributes
-Minimum Operating Temperature 0 C
-Factory Pack Quantity 1250
-Maximum Operating Temperature + 70 C
-Mounting Style SMD/SMT
-Package / Case TQFP-48
-Packaging Tray