ISPPAC-CLK5312S-01TN48I ApplicationField
-Wireless Technology
-Medical Equipment
-Cloud Computing
-Artificial Intelligence
-Consumer Electronics
-Internet of Things
-Industrial Control
-5G Technology
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ISPPAC-CLK5312S-01TN48I FAQ Chips
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ICs ISPPAC-CLK5312S-01TN48I Features
LVPECL, Differential HSTL, Differential SSTL
■ Low Output to Output Skew (<100ps)
■ Up to 20 Programmable Fan-out Buffers
• Non-zero delay buffer with output divider
■ Up to Three Clock Frequency Domains
■ Low Jitter Peak-to-Peak (< 70 ps)
■ 8MHz to 267MHz Input/Output Operation
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
• Zero delay buffer
– LVTTL, LVCMOS, SSTL, HSTL, LVDS,
• Programmable single-ended or differential input reference standards
• Three “Power of 2” output dividers (5-bit)
• Programmable output impedance
(Skew) Per Output
■ Exceptional Power Supply Noise Immunity
• Programmable single-ended output standards and individual enable controls
■ 48-pin and 64-pin TQFP Packages
• Programmable on-chip loop filter
– 1.5V, 1.8V, 2.5V, 3.3V
■ Flexible Clock Reference and External Feedback Inputs
– LVTTL, LVCMOS, SSTL, HSTL
• Programmable slew rate
■ All Inputs and Outputs are Hot Socket Compliant
• Coarse and fine adjustment modes
■ Precision Programmable Phase Adjustment
– LVTTL, LVCMOS, HSTL, eHSTL, SSTL
• Programmable lock detect
• Up to +/- 5ns skew range
• Clock A/B selection multiplexer
– Locked to VCO frequency
■ Full JTAG Boundary Scan Test In-System Programming Support
• Up to 10 banks with individual VCCO and GND
• Zero delay and non-zero delay buffer
• Programmable termination
• Programmable Feedback Standards
■ Fully Integrated High-Performance PLL
– 40 to 70Ω in 5Ω increments
• Internal/external feedback
• Compatible with spread spectrum clocks
• Dual non-zero delay buffer
■ Four Operating Configurations
• 8 settings; minimum step size 156ps
Request ISPPAC-CLK5312S-01TN48I FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx ISPPAC-CLK5312S-01TN48I Overview
ISPPAC-CLK5312S-01TN48I Lattice Semiconductor Corporation, IC CLOCK PROGRAM BUFFER 48TQFP
Zero Delay Buffer 12-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48-Pin TQFP TrayClock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I
The Lattice Clock Drivers & Distribution series ISPPAC-CLK5312S-01TN48I is PLL Based Clock Driver, 5312 Series, 12 True Output(s), 0 Inverted Output(s), PQFP48, LEAD FREE, TQFP-48, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
ISPPAC-CLK5312S-01TN48I Tags integrated circuit
1. ispClock 5300S evaluation kit
2. ispPAC-CLK5312S development board
3. Lattice ispClock 5300S development board
4. ispClock 5300S starter kit
5. ISPPAC-CLK5312S-01TN48I Datasheet PDF
6. Lattice ispPAC-CLK5312S
7. ispClock 5300S ispPAC-CLK5312S
8. ispPAC-CLK5312S reference design
9. ispClock 5300S starter kit
Xilinx ISPPAC-CLK5312S-01TN48I TechnicalAttributes
-Package / Case TQFP-48
-Factory Pack Quantity 1250
-Minimum Operating Temperature – 40℃
-Mounting Style SMD/SMT
-Packaging Tray
-Maximum Operating Temperature + 85℃
