ISPPAC-CLK5320S-01T64C ApplicationField
-5G Technology
-Wireless Technology
-Internet of Things
-Medical Equipment
-Consumer Electronics
-Artificial Intelligence
-Cloud Computing
-Industrial Control
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ISPPAC-CLK5320S-01T64C FAQ Chips
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ICs ISPPAC-CLK5320S-01T64C Features
• Programmable single-ended output standards and individual enable controls
■ Fully Integrated High-Performance PLL
(Skew) Per Output
■ Low Output to Output Skew (<100ps)
• Programmable termination
LVPECL, Differential HSTL, Differential SSTL
• Coarse and fine adjustment modes
• Non-zero delay buffer with output divider
– LVTTL, LVCMOS, SSTL, HSTL, LVDS,
• Three “Power of 2” output dividers (5-bit)
• Programmable output impedance
■ Up to Three Clock Frequency Domains
■ Full JTAG Boundary Scan Test In-System Programming Support
■ All Inputs and Outputs are Hot Socket Compliant
– 40 to 70Ω in 5Ω increments
■ Flexible Clock Reference and External Feedback Inputs
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
• Compatible with spread spectrum clocks
• Programmable Feedback Standards
• Zero delay and non-zero delay buffer
• Programmable slew rate
• Programmable on-chip loop filter
– LVTTL, LVCMOS, SSTL, HSTL
• Dual non-zero delay buffer
• Up to 10 banks with individual VCCO and GND
• Programmable single-ended or differential input reference standards
• Zero delay buffer
• 8 settings; minimum step size 156ps
– 1.5V, 1.8V, 2.5V, 3.3V
■ Precision Programmable Phase Adjustment
■ 8MHz to 267MHz Input/Output Operation
■ Four Operating Configurations
– LVTTL, LVCMOS, HSTL, eHSTL, SSTL
– Locked to VCO frequency
■ Up to 20 Programmable Fan-out Buffers
• Internal/external feedback
■ Exceptional Power Supply Noise Immunity
• Clock A/B selection multiplexer
■ 48-pin and 64-pin TQFP Packages
• Up to +/- 5ns skew range
• Programmable lock detect
■ Low Jitter Peak-to-Peak (< 70 ps)
Request ISPPAC-CLK5320S-01T64C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx ISPPAC-CLK5320S-01T64C Overview
ISPPAC-CLK5320S-01T64C Lattice Semiconductor Corporation, IC BUFFER FANOUT ISP UNIV 64TQFP
Zero Delay Buffer 20-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 64-Pin TQFP Tray
The Lattice Clock & Timer ICs series ISPPAC-CLK5320S-01T64C is PLL Based Clock Driver, 5320 Series, 20 True Output(s), 0 Inverted Output(s), PQFP64, TQFP-64, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
ISPPAC-CLK5320S-01T64C Tags integrated circuit
1. ispPAC-CLK5320S development board
2. Lattice ispClock 5300S development board
3. ispClock 5300S evaluation kit
4. ispClock 5300S starter kit
5. ispClock 5300S ispPAC-CLK5320S
6. Lattice ispPAC-CLK5320S
7. ISPPAC-CLK5320S-01T64C Datasheet PDF
8. ispPAC-CLK5320S evaluation board
9. ispClock 5300S starter kit
Xilinx ISPPAC-CLK5320S-01T64C TechnicalAttributes
-Factory Pack Quantity 800
-Mounting Style SMD/SMT
-Package / Case TQFP-64
-Minimum Operating Temperature 0 C
-Packaging Tray
-Maximum Operating Temperature + 70 C
