ISPPAC-CLK5320S-01TN64C ApplicationField
-Wireless Technology
-5G Technology
-Internet of Things
-Artificial Intelligence
-Medical Equipment
-Consumer Electronics
-Cloud Computing
-Industrial Control
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ICs ISPPAC-CLK5320S-01TN64C Features
LVPECL, Differential HSTL, Differential SSTL
■ Up to 20 Programmable Fan-out Buffers
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
• Internal/external feedback
• Coarse and fine adjustment modes
• Programmable single-ended or differential input reference standards
■ Exceptional Power Supply Noise Immunity
• Zero delay buffer
• Programmable output impedance
• Programmable Feedback Standards
■ Low Output to Output Skew (<100ps)
■ Precision Programmable Phase Adjustment
• Programmable single-ended output standards and individual enable controls
• Clock A/B selection multiplexer
■ Low Jitter Peak-to-Peak (< 70 ps)
• Non-zero delay buffer with output divider
(Skew) Per Output
■ Four Operating Configurations
– LVTTL, LVCMOS, SSTL, HSTL
■ Flexible Clock Reference and External Feedback Inputs
• Compatible with spread spectrum clocks
■ Up to Three Clock Frequency Domains
■ 8MHz to 267MHz Input/Output Operation
• Programmable lock detect
• Programmable slew rate
• Zero delay and non-zero delay buffer
• Up to 10 banks with individual VCCO and GND
• Up to +/- 5ns skew range
■ 48-pin and 64-pin TQFP Packages
• Programmable on-chip loop filter
■ Fully Integrated High-Performance PLL
• Dual non-zero delay buffer
– 40 to 70Ω in 5Ω increments
■ Full JTAG Boundary Scan Test In-System Programming Support
• Three “Power of 2” output dividers (5-bit)
■ All Inputs and Outputs are Hot Socket Compliant
– LVTTL, LVCMOS, SSTL, HSTL, LVDS,
– Locked to VCO frequency
– 1.5V, 1.8V, 2.5V, 3.3V
– LVTTL, LVCMOS, HSTL, eHSTL, SSTL
• Programmable termination
• 8 settings; minimum step size 156ps
Request ISPPAC-CLK5320S-01TN64C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx ISPPAC-CLK5320S-01TN64C Overview
ISPPAC-CLK5320S-01TN64C Lattice Semiconductor Corporation, IC BUFFER FANOUT 20OUTPUT 64TQFP
Zero Delay Buffer 20-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 64-Pin TQFP TrayClock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End
The Lattice Clock Drivers & Distribution series ISPPAC-CLK5320S-01TN64C is Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
ISPPAC-CLK5320S-01TN64C Tags integrated circuit
1. ispClock 5300S evaluation kit
2. ispClock 5300S starter kit
3. Lattice ispClock 5300S development board
4. Lattice ispPAC-CLK5320S
5. ispPAC-CLK5320S evaluation board
6. ispPAC-CLK5320S development board
7. ISPPAC-CLK5320S-01TN64C Datasheet PDF
8. ispPAC-CLK5320S reference design
9. Lattice ispPAC-CLK5320S
Xilinx ISPPAC-CLK5320S-01TN64C TechnicalAttributes
-Type Zero Delay Programmable PLL Clock Generator
-Maximum Power Dissipation 888 mW
-Input Type HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL
-Supply Voltage – Min 3 V
-Factory Pack Quantity 800
-Package / Case TQFP-64
-Max Output Freq 267 MHz
-Supply Current 1.5 mA
-Output Type EHSTL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL
-Minimum Operating Temperature 0 C
-Multiply / Divide Factor 2:20
-Supply Voltage – Max 3.6 V
-Packaging Tray
-Mounting Style SMD/SMT
-Maximum Operating Temperature + 70 C
