ISPPAC-POWR1014A-01TN148I -Internet of Things -Medical Equipment

ISPPAC-POWR1014A-01TN148I ApplicationField

-Industrial Control
-Consumer Electronics
-Artificial Intelligence
-Wireless Technology
-Cloud Computing
-Medical Equipment
-5G Technology
-Internet of Things

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ISPPAC-POWR1014A-01TN148I FAQ Chips 

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ICs ISPPAC-POWR1014A-01TN148I Features

■ Monitor and Control Multiple Power Supplies

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Xilinx ISPPAC-POWR1014A-01TN148I Overview

Lattice’s Power Manager II ispPAC-POWR1014/A is a general-purpose
power-supply monitor and sequence controller, incorporating both in-system
programmable logic and in-system programmable analog functions implemented in
non-volatile E2 CMOS technology. The ispPAC-POWR1014/A device provides 10
independent analog input channels to monitor up to 10 power supply test points.
Each of these input channels has two independently programmable comparators to
support both high/low and in-bounds/out-of-bounds (window-compare) monitor
functions. Four general-purpose digital inputs are also provided for
miscellaneous control functions.

The ispPAC-POWR1014/A provides 14 open-drain
digital outputs that can be used for controlling DC-DC converters, low-drop-out
regulators (LDOs) and optocouplers, as well as for supervisory and
general-purpose logic interface functions. Two of these outputs (HVOUT1-HVOUT2)
may be configured as high-voltage MOSFET drivers. In high-voltage mode these outputs can provide up to 10V for
driving the gates of n-channel MOSFETs so that they can be used as high-side
power switches controlling the supplies with a programmable ramp rate for both
ramp up and ramp down.

The ispPAC-POWR1014/A incorporates a 24-macrocell CPLD
that can be used to implement complex state machine sequencing for the control
of multiple power supplies as well as combinatorial logic functions. The status
of all of the comparators on the analog input channels as well as the general
purpose digital inputs are used as inputs by the CPLD array, and all digital
outputs may be controlled by the CPLD. Four independently programmable timers
can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is
programmed using LogiBuilder, an easy-to-learn language integrated into the
PAC-Designer software. Control sequences are written to monitor the status of
any of the analog input channel comparators or the digital inputs.

The on-chip
10-bit A/D converter is used to monitor the VMON voltage through the I2 C bus of
the ispPACPOWR1014A device.

The I2 C bus/SMBus interface allows an external
microcontroller to measure the voltages connected to the VMON inputs, read back
the status of each of the VMON comparator and PLD outputs, control logic signals
IN2 to IN4 and control the output pins (ispPAC-POWR1014A only).

ISPPAC-POWR1014A-01TN148I Tags integrated circuit

1. Lattice ispPAC-POWR development board
2. ispPAC-POWR starter kit
4. ISPPAC-POWR1014 reference design
5. ISPPAC-POWR1014 evaluation board
6. Lattice ISPPAC-POWR1014
7. ispPAC-POWR evaluation kit
8. ISPPAC-POWR1014 development board
9. ISPPAC-POWR1014 reference design

Xilinx ISPPAC-POWR1014A-01TN148I TechnicalAttributes

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