ISPPAC-POWR1220AT8-02TN -Internet of Things -5G Technology

ISPPAC-POWR1220AT8-02TN ApplicationField

-Medical Equipment
-Industrial Control
-Cloud Computing
-Consumer Electronics
-Wireless Technology
-5G Technology
-Artificial Intelligence
-Internet of Things

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ICs ISPPAC-POWR1220AT8-02TN Features

 Monitor, Control, and Margin Multiple Power Supplies

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Xilinx ISPPAC-POWR1220AT8-02TN Overview

The Lattice Power Manager II ispPAC-POWR1220AT8 is a general-purpose
power-supply monitor, sequence and margin controller, incorporating both
in-system programmable logic and in-system programmable analog functions
implemented in non-volatile E2 CMOS technology. The ispPAC-POWR1220AT8 device
provides 12 independent analog input channels to monitor up to 12 power supply
test points. Each of these input channels offers a differential input to support
remote ground sensing, and has two independently programmable comparators to
support both high/low and in-bounds/ out-of-bounds (window-compare) monitor
functions. Six general-purpose digital inputs are also provided for
miscellaneous control functions.

The ispPAC-POWR1220AT8 provides 20 open-drain
digital outputs that can be used for controlling DC-DC converters, low-drop-out
regulators (LDOs) and optocouplers, as well as for supervisory and
general-purpose logic interface functions. Four of these outputs (HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers. In
high-voltage mode these outputs can provide up to 12V for driving the gates of
n-channel MOSFETs so that they can be used as high-side power switches
controlling the supplies with a programmable ramp rate for both ramp up and ramp

The ispPAC-POWR1220AT8 incorporates a 48-macrocell CPLD that can be used
to implement complex state machine sequencing for the control of multiple power
supplies as well as combinatorial logic functions. The status of all of the
comparators on the analog input channels as well as the general purpose digital
inputs are used as inputs by the CPLD array, and all digital outputs may be
controlled by the CPLD. Four independently programmable timers can create delays
and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using
LogiBuilder, an easy-to-learn language integrated into the PAC-Designer
software. Control sequences are written to monitor the status of any of the
analog input channel comparators or the digital inputs.

In addition to the
sequence control functions, the ispPAC-POWR1220AT8 incorporates eight DACs for
generating trimming voltage to control the output voltage of a DC-DC converter.
The trimming voltage can be set to four hardware selectable preset values
(voltage profiles) or can be dynamically loaded in to the DAC through the I2 C
bus. Additionally, each power supply output voltage can be maintained typically
within 0.5% tolerance across various load conditions using the Digital Closed
Loop Control mode. The operating voltage profile can either be selected using
external hardware pins or through the PLD outputs.

The on-chip 10-bit A/D
converter can both be used to monitor the VMON voltage through the I2 C bus as
well as for implementing digital closed loop mode for maintaining the output
voltage of all power supplies controlled by the monitoring and trimming section
of the ispPAC-POWR1220AT8 device.

The I2 C bus/SMBus interface allows an
external microcontroller to measure the voltages connected to the VMON inputs,
read back the status of each of the VMON comparator and PLD outputs, control
logic signals IN2 to IN5, control the output pins, and load the DACs for the
generation of the trimming voltage of the external DC-DC converter.

ISPPAC-POWR1220AT8-02TN Tags integrated circuit

1. Lattice ISPPAC-POWR1220A
2. ispPAC-POWR evaluation kit
3. ISPPAC-POWR1220AT8-02TN Datasheet PDF
4. Lattice ispPAC-POWR development board
5. ispPAC-POWR starter kit
6. ISPPAC-POWR1220A development board
7. ISPPAC-POWR1220A reference design
8. ISPPAC-POWR1220A evaluation board
9. Lattice ispPAC-POWR development board

Xilinx ISPPAC-POWR1220AT8-02TN TechnicalAttributes

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