ISPPAC-POWR607-01NN32I ApplicationField
-Internet of Things
-Medical Equipment
-Artificial Intelligence
-Wireless Technology
-Industrial Control
-Cloud Computing
-Consumer Electronics
-5G Technology
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ISPPAC-POWR607-01NN32I FAQ Chips
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ICs ISPPAC-POWR607-01NN32I Features
Power-Down Mode ICC < 10 µA
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Xilinx ISPPAC-POWR607-01NN32I Overview
The Power Manager II ispPAC-POWR607 is a generalpurpose power-supply monitor,
reset generator and watchdog timer, incorporating both in-system programmable
logic and analog functions implemented in nonvolatile E2 CMOS technology. The
ispPAC-POWR607 device provides six independent analog input channels to monitor
power supply voltages. Two general-purpose digital inputs are also provided for
miscellaneous control functions.
The ispPAC-POWR607 provides up to seven
open-drain digital outputs that can be used for controlling DC-DC converters,
low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and
general-purpose logic interface functions. Two of these outputs (HVOUT1-HVOUT2) can be configured as high-voltage MOSFET drivers. In
high-voltage mode these outputs provide 9V for driving the gates of n-channel
MOSFETs used as high-side power switches to control power supply ramp up and
ramp down rate. The remaining five digital, open drain outputs can optionally be
configured as digital inputs to sense more input signals as needed, such as
manual reset, etc.
The diagram above shows how a ispPAC-POWR607 is used in a
typical application. It controls power to the microprocessor system, generates
the CPU reset and monitors critical power supply voltages, generating interrupts
whenever faults are detected. It also provides a watchdog timer function to
detect CPU operating and bus timeout errors.
The ispPAC-POWR607 incorporates a
16-macrocell CPLD. Figure 1 shows the analog input comparators and digital
inputs used as inputs to the CPLD array. The digital output pins providing the
external control signals are driven by the CPLD. Four independently program mable timers also interface with the CPLD and can create delays and time-outs
ranging from 32µs to 2 seconds. The CPLD is programmed using LogiBuilder, an
easy-to-learn language integrated into the PAC-Designer software. Control
sequences are written to monitor the status of any of the analog input channel
comparators or the digital inputs.
The Lattice Power Management ICs series ISPPAC-POWR607-01NN32I is Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. I, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
ISPPAC-POWR607-01NN32I Tags integrated circuit
1. Lattice ispPAC-POWR development board
2. ISPPAC-POWR607-01NN32I Datasheet PDF
3. Lattice ISPPAC-POWR607
4. ispPAC-POWR evaluation kit
5. ISPPAC-POWR607 evaluation board
6. ispPAC-POWR starter kit
7. ISPPAC-POWR607 reference design
8. ispPAC-POWR ISPPAC-POWR607
9. ispPAC-POWR evaluation kit
Xilinx ISPPAC-POWR607-01NN32I TechnicalAttributes
-Number of Voltages Monitored 6
-Supply Current (Typ) 3.5 mA
-Package / Case QFN-32
-Watchdog Watchdog
-Mounting Style SMD/SMT
-Packaging Tray
-Overvoltage Threshold Adjustable
-Minimum Operating Temperature – 40℃
-Factory Pack Quantity 2450
-Undervoltage Threshold 0.8 V
-Output Type Open Collector / Drain
-Power-Up Reset Delay (Typ) 300 us
-Maximum Operating Temperature + 85℃
-Supply Voltage – Max 3.96 V
-Supply Voltage – Min 2.64 V
-Manual Reset Resettable
