ISPPAC-POWR6AT6-01NN32I -Wireless Technology -Internet of Things

ISPPAC-POWR6AT6-01NN32I ApplicationField

-5G Technology
-Industrial Control
-Consumer Electronics
-Artificial Intelligence
-Cloud Computing
-Internet of Things
-Medical Equipment
-Wireless Technology

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ISPPAC-POWR6AT6-01NN32I FAQ Chips 

Q: Does the price of ISPPAC-POWR6AT6-01NN32I devices fluctuate frequently?
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A: RAYPCB does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.

Q: How can I obtain software development tools related to the Lattice FPGA platform?
A: Lattice’s development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.

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ICs ISPPAC-POWR6AT6-01NN32I Features

■ Power Supply Margin and Trim Functions

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Xilinx ISPPAC-POWR6AT6-01NN32I Overview

Lattice’s Power Manager II ISPPAC-POWR6AT6-01NN32I is a general-purpose power-supply
monitoring and margining controller, incorporating in-system programmable analog
functions implemented in non-volatile E2 CMOS technology. The ISPPAC-POWR6AT6-01NN32I
device provides six independent analog input channels to monitor up to six power
supply test points. Each of these input channels offers a differential input to
support remote ground sensing.

The ISPPAC-POWR6AT6-01NN32I incorporates six DACs for
generating a trimming voltage to control the output voltage of a power supply.
The trimming voltage can be set to four hardware selectable preset values
(voltage profiles) or can be dynamically loaded in to the DAC through the I 2 C
bus. Additionally, each power supply output voltage can be maintained typically
within 0.5% tolerance across various load conditions using the Digital Closed
Loop Control mode. The operating voltage profile can be selected using external
hardware pins.

The on-chip 10-bit A/D converter can both be used to monitor the VMON voltage
through the I2 C bus as well as for implementing digital closed loop mode for
maintaining the output voltage of all power supplies controlled by the
monitoring and trimming section of the ispPACPOWR6AT6 device.

The I2 C bus/SMBus
interface allows an external microcontroller to measure the voltages connected
to the VMON analog monitor inputs and load the DACs for the generation of the
trimming voltages of the external DCDC converters.

The Lattice Power Management ICs series ISPPAC-POWR6AT6-01NN32I is Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.

ISPPAC-POWR6AT6-01NN32I Tags integrated circuit

1. ispPAC-POWR starter kit
2. ispPAC-POWR6AT6 development board
3. Lattice ispPAC-POWR development board
4. ispPAC-POWR6AT6 evaluation board
5. ISPPAC-POWR6AT6-01NN32I Datasheet PDF
6. ispPAC-POWR evaluation kit
7. ispPAC-POWR ispPAC-POWR6AT6
8. Lattice ispPAC-POWR6AT6
9. ispPAC-POWR6AT6 evaluation board

Xilinx ISPPAC-POWR6AT6-01NN32I TechnicalAttributes

-Package / Case QFN-32
-Minimum Operating Temperature – 40℃
-Number of Voltages Monitored 6
-Overvoltage Threshold Adjustable
-Mounting Style SMD/SMT
-Factory Pack Quantity 2450
-Packaging Tray
-Supply Voltage – Max 3.96 V
-Power-Up Reset Delay (Typ) 500 ms
-Undervoltage Threshold Adjustable
-Supply Voltage – Min 2.8 V
-Watchdog No Watchdog
-Maximum Operating Temperature + 85℃
-Supply Current (Typ) 10 mA

-Manual Reset Not Resettable
-Monitored Voltage – 0.3 V to 5.9 V
-Output Type Open Collector / Drain

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