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LFE5UM5G-85F-8MG285I FAQ Chips
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ICs LFE5UM5G-85F-8MG285I Features
Advanced 18 x 36 MAC and 18 x 18 Multiply-Multiply-Accumulate (MMAC) operations
194K to 669K bits distributed RAM
Single Event Upset (SEU) Mitigation Support
Higher Logic Density for Increased System Integration
197 to 365 user programmable I/O
Source synchronous standards support
DDR registers in I/O cells
Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate
Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI
12K to 84K LUTs
Pre-Engineered Source Synchronous I/O
LVTTL and LVCMOS 33/25/18/15/12
270 Mb/s, up to 3.2 Gb/s, SERDES interface(ECP5)
Powerful 54-bit ALU operations
LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
Soft Error Correction – Without stopping user operation
Time Division Multiplexing MAC Sharing
12 to 160 slices for high performance multiply and accumulate
High Speed ADC/DAC devices
SSTL 18/15 I, II
SPI boot flash interface
Supports eDP in RDR (1.62 Gb/s) and HDR (2.7 Gb/s)
subLVDS and SLVS, SoftIP MIPI D-PHY receiver/transmitter interfaces
On-chip oscillator for initialization and general use
Programmable sysI/O Buffer Supports Wide Range of Interfaces
ADC/DAC, 7:1 LVDS, XGMII
Shared bank for configuration I/O
IEEE 1149.1 and IEEE 1532 compliant
Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers
sysCLOCK Analog PLLs and DLLs
Flexible Memory Resources
Up to 3.744 Mb sysMEM Embedded Block RAM (EBR)
Dedicated read/write levelling functionality
Rounding and truncation
Soft Error Injection – Emulate SEU event to debug system error handling
TransFR I/O for simple field updates
Dedicated gearing logic
Reveal Logic Analyzer
Soft Error Detect – Embedded hard macro
270 Mb/s, up to 5.0 Gb/s, SERDES interface(ECP5-5G)
System Level Support
Dual-boot images supported
1.1 V core power supply for ECP5, 1.2 V core power supply for ECP5UM5G
Flexible Device Configuration
Each slice supports
Four DLLs and four PLLs in LFE5-45 and LFE5-85; two DLLs and two PLLs in LFE5-25 and LFE5-12
Fully cascadable slice architecture
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Xilinx LFE5UM5G-85F-8MG285I Overview
The LFE5UM5G-85F-8MG285I devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 40 nm technology making the devices suitable for high-volume, highspeed, and low-cost applications.
The LFE5UM5G-85F-8MG285I covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 user I/O. The LFE5UM5G-85F-8MG285I device family also offers up to 156 18 x 18 multipliers and a wide range of parallel I/O standards. The ECP5/ECP5-5G FPGA fabric is optimized high performance with low power and low cost in mind. The LFE5UM5G-85F-8MG285I devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distributed and embedded memory, Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities.
The pre-engineered source synchronous logic implemented in the ECP5/ECP5-5G device family supports a broad range of interface standards including DDR2/3, LPDDR2/3, XGMII, and 7:1 LVDS. The LFE5UM5G-85F-8MG285I also features high speed SERDES with dedicated Physical Coding Sublayer (PCS) functions. High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit De-emphasis with pre- and post-cursors, and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media.
The LFE5UM5G-85F-8MG285I devices also provide flexible, reliable and secure configuration options, such as dual-boot capability, bit-stream encryption, and TransFR field upgrade features. ECP5-5G family devices have made some enhancement in the SERDES compared to ECP5UM devices. These enhancements increase the performance of the SERDES to up to 5 Gb/s data rate.The LFE5UM5G-85F-8MG285I devices are pin-to-pin compatible with the ECP5UM devices. These allows a migration path for you to port designs from ECP5UM to ECP5-5G devices to get higher performance.
The Lattice Diamond design software allows large complex designs to be efficiently implemented using the ECP5/ECP5-5G FPGA family. Synthesis library support for ECP5/ECP5-5G devices is available for popular logic synthesis tools. The Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LFE5UM5G-85F-8MG285I device. The tools extract the timing from the routing and back-annotate it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) modules for the LFE5UM5G-85. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
The Lattice Embedded – FPGAs (Field Programmable Gate Array) series LFE5UM5G-85F-8MG285I is IC FPGA 118 I/O 285CSFBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
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LFE5UM5G-85F-8MG285I Tags integrated circuit
1. Lattice LFE5UM5G-85
2. ECP5 evaluation kit
3. LFE5UM5G-85 development board
4. ECP5 LFE5UM5G-85
5. LFE5UM5G-85 reference design
6. Lattice ECP5 development board
7. LFE5UM5G-85 evaluation board
8. ECP5 starter kit
9. ECP5 LFE5UM5G-85
Xilinx LFE5UM5G-85F-8MG285I TechnicalAttributes
-Mounting Type Surface Mount
-Supplier Device Package 285-CSFBGA (10×10)
-Number of LABs/CLBs 21000
-Number of Logic Elements/Cells 84000
-Total RAM Bits 3833856
-Operating Temperature -40℃ ~ 100℃ (TJ)
-Number of I/O 118
-Package / Case 285-TFBGA
-Voltage – Supply 1.045V ~ 1.155V