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LPTM21L-1ABG100I FAQ Chips
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Q: How can I obtain software development tools related to the Lattice FPGA platform?
A: Lattice’s development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
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A: RAYPCB does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
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ICs LPTM21L-1ABG100I Features
Ten Rail Voltage Monitoring and
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Xilinx LPTM21L-1ABG100I Overview
The Lattice Platform Manager 2 device is a fast-reacting, programmable logic based hardware management controller. Platform Manager 2 is an integrated solution combining analog sense and control elements with scalable
programmable logic resources. This unique approach allows Platform Manager 2 to integrate Power Management
(Power Sequencing, Voltage Monitoring, Trimming and Margining), Thermal Management (Temperature Monitoring, Fan Control, Power Control), and Control Plane functions (System Configuration, I/O Expansion, etc.) as a single device.
Architecturally, the Platform Manager 2 device can be divided into two sections – Analog Sense and Control and
FPGA. The Analog Sense and Control (ASC) section provides three types of analog sense channels: voltage (nine
standard channels and one high voltage channel), current (one standard voltage and one high voltage) and temperature (two external and one internal).
Each of the analog sense channels is monitored through two independently programmable comparators to support
both high/low and in-bounds/out-of-bounds (window-compare) monitor functions. In addition, each of the current
sense channels provides a fast fault detect (one µs response time) for detecting short circuit events. The temperature sense channels can be configured to work with different external transistor or diode configurations.
The Analog Sense and Control section also provides ten general purpose 5 V tolerant open-drain digital input/output pins that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and opto-couplers, as
well as for general purpose logic interface functions. In addition, four high-voltage charge pumped outputs
(HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers to control high-side MOSFET switches.
These HVOUT outputs can also be programmed as static output signals or as switched outputs (to support external charge pump implementation) operating at a dedicated duty cycle and frequency
The ASC section incorporates four TRIM outputs for controlling the output voltages of DC-DC converters. Each
power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using
the Digital Closed Loop Control mode of the trimming block.
The internal 10-bit A/D converter can be used to measure the voltage and current through the I2
C bus. The ADC is
also used in the digital closed loop control mode of the trimming block.
The ASC section also provides the capability of logging up to 16 status records into its nonvolatile EEPROM memory. Each record includes voltage, current and temperature monitor signals along with digital input and output levels.
The ASC section includes an output control block (OCB) which allows certain inputs and control signals a direct
connection to the digital outputs or HVOUTs, bypassing the ASC-I/F for a faster response. The OCB is used to connect the fast current fault detect signal to an FPGA input directly. It also supports functions such as Hot Swap with
a programmable hysteretic controller.
The FPGA section contains non-volatile low cost programmable logic of 1280 Look-Up Tables (LUTs). In addition to
the LUT-based logic, the FPGA section features Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), flexible I/Os, and hardened versions of commonly used functions such as SPI controller, I2
and Timer/counter. The FPGA I/Os offer enhanced features such as drive strength control, slew rate control, buskeeper latches, internal pull-up or pull-down resistors, and open-drain outputs. These features are controllable on a
The power management, thermal management and control plane logic functions are implemented in the FPGA
section of Platform Manager 2. The FPGA receives the analog comparator values and inputs from the ASC section
and sends output commands to the ASC section through the dedicated ASC-interface (ASC-I/F) high-speed, reliable serial channel. The FPGA hardware management functions are implemented using the Platform Designer tool
inside Lattice Diamond software. The Platform Designer tool includes an easy to use sequence and monitor logic builder tool and a set of pre-engineered components for functions like time-stamped fault logging, voltage by identification (VID), and fan control.
The Platform Manager 2 is designed to enable seamless scaling of the number of voltage, current and temperature
sense channels in the system by adding external Hardware Management Expanders. Hardware Management
Expanders can be realized with either the Analog Sense and Control (ASC) L-ASC10 device or the LPTM21L (100-
Ball caBGA package) device. The algorithm implemented within the FPGA section can access and control these
external ASCs through the dedicated ASC-I/F. Larger systems with up to eight expanders can be created by using
a MachXO2, MachXO3, or ECP5 FPGA in place of the Platform Manager 2 device. The expander devices are connected in a scalable, star topology to Platform Manager 2, MachXO2, MachXO3, or ECP5.
The Platform Manager 2 has an I2
C interface which is used by the FPGA section for ASC interface configuration.
C interface also provides the mechanism for parameter measurement or I/O control or status. For example,
voltage trim targets can be set over the I2
C bus and measured voltage, current, or temperature values can be read
over the I2
The Platform Manager 2 device can be programmed in-system through JTAG or I2
C interfaces. The configuration is
stored in on-chip non-volatile memory. Upon power-on, the FPGA section configuration is transferred to the on-chip
SRAM and the device operates from SRAM. It is possible to update the non-volatile memory content in the background without interrupting the system operation.
LPTM21L-1ABG100I Tags integrated circuit
1. LPTM21L-1ABG100I Datasheet PDF
2. Lattice Platform Manager 2 development board
3. Lattice LPTM21
4. Platform Manager 2 evaluation kit
5. Platform Manager 2 LPTM21
6. LPTM21 evaluation board
7. LPTM21 reference design
8. Platform Manager 2 starter kit
9. Platform Manager 2 evaluation kit
Xilinx LPTM21L-1ABG100I TechnicalAttributes
-Supplier Device Package 100-CABGA (10×10)
-Mounting Type Surface Mount
-Operating Temperature -40℃ ~ 100℃ (TJ)
-Package / Case 100-LFBGA
-Current – Supply 25mA
-Voltage – Supply 4.75V ~ 13.2V
-Applications Hardware Management Controller