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M5-512/160-15YC FAQ Chips
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ICs M5-512/160-15YC Features
◆ High logic densities and I/Os for increased logic integration
Request M5-512/160-15YC FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx M5-512/160-15YC Overview
The MACH 5 family consists of a broad range of high-density and high-I/O Complex
Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds
at high CPLD densities, low power, and supports additional features such as in-system
programmability, Boundary Scan testability, and advanced clocking options . The MACH
5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process
technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns . The
5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification.
With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512
macrocells to support full system logic integration. Extensive routing resources ensure pinout
retention as well as high utilization. It is ideal for PAL block device integration and a wide range
of other applications including high-speed computing, low-power applications, communications,
and embedded control. At each macrocell density point, Lattice offers several I/O and package
options to meet a wide range of design needs.
Advanced power management options allow designers to incrementally reduce power while
maintaining the level of performance needed for today’s complex designs. I/O safety features
allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system
programmable through an IEEE 1149.1 Test Access Port (TAP) interface.
The Lattice CPLD – Complex Programmable Logic Devices series M5-512/160-15YC is Fifth Generation MACH Architecture,CPLD – Complex Programmable Logic Devices Use ispMACH 4000V or M4A5, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
M5-512/160-15YC Tags integrated circuit
1. M5-512 reference design
2. MACH 5 CPLD M5-512
3. M5-512 development board
4. Lattice M5-512
5. MACH 5 CPLD starter kit
6. M5-512 evaluation board
7. Lattice MACH 5 CPLD development board
8. MACH 5 CPLD evaluation kit
9. Lattice M5-512
Xilinx M5-512/160-15YC TechnicalAttributes
-Minimum Operating Temperature 0 C
-Number of Programmable I/Os 160
-Supply Voltage – Max 5.25 V
-Memory Type EEPROM
-Supply Voltage – Min 4.75 V
-Number of Macrocells 512
-Operating Supply Voltage 4.75 V to 5.25 V
-Delay Time 15 ns
-Package / Case PQFP-208
-Number of Product Terms per Macro 32
-Mounting Style SMD/SMT
-Maximum Operating Temperature + 70 C
-Factory Pack Quantity 120
-Maximum Operating Frequency 71.4 MHz, 83.3 MHz