ORSO42G52BM484C-1BM484I ApplicationField
-Industrial Control
-Wireless Technology
-Medical Equipment
-Consumer Electronics
-Cloud Computing
-5G Technology
-Artificial Intelligence
-Internet of Things
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ICs ORSO42G52BM484C-1BM484I Features
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Xilinx ORSO42G52BM484C-1BM484I Overview
The ORSO42G52BM484C-1BM484I and ORSO82G5 support a clockless high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORSO42G52BM484C-1BM484I and ORSO82G5 allows higher system performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. Network designers will benefifit from using the backplane transceiver as a network termination device. Sister devices, the ORT42G5 and the ORT82G5, support 8b/10b encoding/decoding and link state machines for 10 Gbit Ethernet (XAUI) and Fibre Channel. The ORSO42G52BM484C-1BM484I and ORSO82G5 perform SONET data scrambling/descrambling, streamlined SONET framing, limited Transport OverHead (TOH) handling, plus the programmable logic to terminate the network into proprietary systems. The cell processing feature in the ORSO42G52BM484C-1BM484I and ORSO82G5 makes them ideal for interfacing devices with any proprietary data format across a high-speed backplane. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. The ORSO42G52BM484C-1BM484I and ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.
ORSO42G52BM484C-1BM484I Tags integrated circuit
1. ORSO42G5 reference design
2. ORSO42G5 development board
3. Lattice ORSO42G5
4. ORSO42G5 evaluation board
5. FPGA ORCA Series 4 evaluation kit
6. FPGA ORCA Series 4 ORSO42G5
7. Lattice FPGA ORCA Series 4 development board
8. ORSO42G52BM484C-1BM484I Datasheet PDF
9. ORSO42G5 evaluation board
Xilinx ORSO42G52BM484C-1BM484I TechnicalAttributes