XC17128EVO8C ApplicationField
-Cloud Computing
-Industrial Control
-Consumer Electronics
-Artificial Intelligence
-Wireless Technology
-5G Technology
-Medical Equipment
-Internet of Things
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XC17128EVO8C FAQ Chips
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Q: How can I obtain software development tools related to the Xilinx FPGA platform?
A: In FPGA/CPLD design tools, Xilinx’s Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
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ICs XC17128EVO8C Features
Simple interface to the FPGA; requires only one user I/O pin
One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGAs
XC17128E/EL, XC17256E/EL, XC1701, and XC1700L series support fast configuration
Guaranteed 20 year life data retention
Low-power CMOS floating-gate process
Available in compact plastic packages: 8-pin SOIC, 8- pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44- pin PLCC or 44-pin VQFP
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions
XC1700L series are available in 3.3V only
Lead-free (Pb-free) packaging available
Design support using the Xilinx Alliance and Foundation software packages
Programming support by leading programmer manufacturers
XC1700E series are available in 5V and 3.3V versions
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Xilinx XC17128EVO8C Overview
The XC17128EVO8C provides an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. After configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal.Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The XC17128EVO8C inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family.For device programming, either the Xilinx Alliance or Foundation software compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.
The Xilinx Memory – Configuration Proms for FPGA's series XC17128EVO8C is PROM Serial 128Kbit 5V 8Pin TSOP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC17128EVO8C Tags integrated circuit
1. XC17128EVO8C Datasheet PDF
2. XC17128E reference design
3. Memory – Configuration Proms for FPGA’s starter kit
4. XC17128E development board
5. Xilinx Memory – Configuration Proms for FPGA’s development board
6. Memory – Configuration Proms for FPGA’s XC17128E
7. Memory – Configuration Proms for FPGA’s evaluation kit
8. XC17128E evaluation board
9. XC17128E development board
Xilinx XC17128EVO8C TechnicalAttributes
-Voltage – Supply 4.75V ~ 5.25V
-Memory Size 128kb
-Package / Case 8-SOIC (0.154, 3.90mm Width)
-Operating Temperature 0℃ ~ 70℃
-Supplier Device Package 8-TSOP
-Programmable Type OTP
