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XC2C384-10FGG324I FAQ Chips
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ICs XC2C384-10FGG324I Features
• In-System Programmable PROMs for Configuration of Xilinx FPGAs
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Xilinx XC2C384-10FGG324I Overview
The XC2C384-10FGG324I device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.This XC2C384-10FGG324I device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device.The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O standards. This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK featureDataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the XC2C384-10FGG324I device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.
The Xilinx Embedded – CPLDs (Complex Programmable Logic Devices) series XC2C384-10FGG324I is 384 MACROCELL 1.8V ZERO POWER ISP CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC2C384-10FGG324I Tags integrated circuit
1. Xilinx XC2C384
2. CoolRunner-II CPLD starter kit
3. XC2C384-10FGG324I Datasheet PDF
4. CoolRunner-II CPLD XC2C384
5. XC2C384 evaluation board
6. Xilinx CoolRunner-II CPLD development board
7. CoolRunner-II CPLD evaluation kit
8. XC2C384 development board
9. CoolRunner-II CPLD XC2C384
Xilinx XC2C384-10FGG324I TechnicalAttributes
-Number of Logic Elements/Blocks 24
-Number of Macrocells 384
-Voltage Supply – Internal 1.7V ~ 1.9V
-Number of I/O 240
-Operating Temperature -40℃ ~ 85℃ (TA)
-Mounting Type Surface Mount
-Package / Case 324-BBGA
-Supplier Device Package 324-FBGA (23×23)
-Programmable Type In System Programmable
-Delay Time tpd(1) Max 9.2ns
-Number of Gates 9000