XC3S5000-5FG900C ApplicationField
-Internet of Things
-Artificial Intelligence
-Cloud Computing
-5G Technology
-Consumer Electronics
-Industrial Control
-Wireless Technology
-Medical Equipment
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XC3S5000-5FG900C FAQ Chips
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ICs XC3S5000-5FG900C Features
• Logic resources
– Up to 1,728 Kbits of total block RAM
– Double Data Rate (DDR) support
– Up to 633 I/O pins
• Eight global clock lines and abundant routing
– Fast look-ahead carry logic
– Eight differential signal standards including LVDS
– Wide multiplexers
– Abundant logic cells with shift register capability
• SelectIO signaling
– JTAG logic compatible with IEEE 1149.1/1532
– Frequency synthesis
and RSDS
– Clock skew elimination
– High-resolution phase shifting
– Eighteen single-ended signal standards
– Dedicated 18 x 18 multipliers
– Up to 432 Kbits of total distributed RAM
• SelectRAM hierarchical memory
• Digital Clock Manager (four DCMs)
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Xilinx XC3S5000-5FG900C Overview
Introduction:
The Spartan®-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to 5,000,000 system gates, as shown in Table 1. The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex®-II platform technology. These Spartan-3 FPGA enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously
possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment. The Spartan-3 family is a superior alternative to mask rogrammed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.
Module 1:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013
• Introduction
• Features
• Architectural Overview
• Array Sizes and Resources
• User I/O Chart
• Ordering Information
Module 2: Functional Description
DS099 (v3.1) June 27, 2013
• Input/Output Blocks (IOBs)
• IOB Overview
• SelectIO™ Interface I/O Standards
• Configurable Logic Blocks (CLBs)
• Block RAM
• Dedicated Multipliers
• Digital Clock Manager (DCM)
• Clock Network
• Configuration
Module 3:
DC and Switching Characteristics
DS099 (v3.1) June 27, 2013
• DC Electrical Characteristics
• Absolute Maximum Ratings
• Supply Voltage Specifications
• Recommended Operating Conditions
• DC Characteristics
• Switching Characteristics
• I/O Timing
• Internal Logic Timing
• DCM Timing
• Configuration and JTAG Timing
The Xilinx FPGAs series XC3S5000-5FG900C is FPGA Spartan-3 Family 5M Gates 74880 Cells 725MHz 90nm Technology 1.2V 900-Pin F-BGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC3S5000-5FG900C Tags integrated circuit
1. XC3S5000 evaluation board
2. Spartan-3 FPGA starter kit
3. XC3S5000 reference design
4. XC3S5000-5FG900C Datasheet PDF
5. Xilinx Spartan-3 FPGA development board
6. Xilinx XC3S5000
7. Spartan-3 FPGA XC3S5000
8. Spartan-3 FPGA evaluation kit
9. XC3S5000-5FG900C Datasheet PDF
Xilinx XC3S5000-5FG900C TechnicalAttributes
-Mounting Type Surface Mount
-Number of I/O 633
-Voltage – Supply 1.14V ~ 1.26V
-Total RAM Bits 1916928
-Number of LABs/CLBs 8320
-Number of Logic Elements/Cells 74880
-Package / Case 900-BBGA
-Operating Temperature 0℃ ~ 85℃ (TJ)
-Number of Gates 5000000
-Supplier Device Package 900-FBGA (31×31)