Xilinx FPGA

What is XILINX XC3S700A-4FGG484I FPGA

XC3S700A-4FGG484I hails from the family of Spartan-3A. These devises come up with the body size of 23×23 mm. XC3S700A-4FGG484I device offers 372 user I/O and input only pins with the option of offering 165 user input only pins. On the other hand, these devices offer 142 differential I/O and input only pins while 93 differential input pins only. XC3S700A-4FGG484I device contains 484-ball FBGA Array. 484-ball FBGA pins of these devices can tolerate an industrial temperature range from -40 °C to 100 °C. These are very economical device exhibiting superior performance in various applications such as electronics, broadband technology etc. These devices are programmed for different industrial standards

XC3S700A-4FGG484I Properties:

As explained earlier, XC3S700A-4FGG484I devices come up with Fine pitch Ball Grid Array also known as FBGA Array. These devices contains 484 leads with maximum I/O of 372 and Lead Pitch of 1 mm. XC3S700A-4FGG484I device body area is around 23  by 23 mm and height up to 2.60 mm. XC3S700A-4FGG484I devices contain 5 GND Pairs in each of the 4 banks. These devices specifically FG484 package offers power and ground supply pins as VCCINT (15), VCCAUX (10), VCCO (24), and GND (23). The device consists of 700K system gates having 13,248 equivalent logic cells.  XC3S700A-4FGG484I device consists of 1,472 Configurable Logic Control array with 4 slices. The device comes up with 72K Distributed RAM bits having 360K blocked RAM bits. XC3S700A-4FGG484I is equipped with 20 dedicated multipliers having 8 Digital Clock Managers (DCM). These devices are designed for Quiescent current supply of 120 mA (commercial maximum) and 185 mA (industrial maximum).

I/O Timings:

Having maximum I/O of 372, XC3S700A-4FGG484I contains 4 banks with distribution of I/O as 92, 94, 92 and 94 on Top, Right, Bottom and Left edge of the package. Pins T8, U7 and U16 can easily migrate from left device to the right device without any condition.

Clock to Output timings of XC3S700A-4FGG484I devices are optimized from 3.39 ns to 3.50 ns with Digital Clock Manager (DCM) is in use. Similarly, these devices are optimized at output timing from 4.97 ns to 5.34 ns with no Digital Clock Manager in use. It is important to note here that Digital Clock Manager jitter is inclusive in all of the above measurements.

Pin to Pin setup times for the IOB input path for XC3S700A-4FGG484I devices ranges from 2.38 ns to 2.57 ns when the Digital Clock Manager (DCM) is in use with no configured Input delay. While pin to pin setup times for the same device ranges from 2.28 ns to 2.63 ns when no Digital Clock Manager (DCM) is in use with programmed input delay. On the other hand, Hold time for XC3S700A-4FGG484I devices ranges from -0.17 ns to -0.12 ns when DCM is in use with no programmed input delay and Hold time ranges from -0.80 ns to -0.74 ns when no DCM is in use with programmed input delay.

Clock Timing:

All XC3S700A-4FGG484I devices has the frequency of TCK signal clocked at 0 MHz (minimum) to 20 MHz (maximum).

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