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XC95108-15PQG100I FAQ Chips
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ICs XC95108-15PQG100I Features
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Xilinx XC95108-15PQG100I Overview
The XC95108-15PQG100I is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 108 macrocells with 2,400 usable gates
• Up to 108 user I/O pins
• 5V in-system programmable
– Endurance of 10,000 program/erase cycles
– Program/erase over full commercial voltage and temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
– 90 product terms drive any or all of 18 macrocells
within Function Block
– Global and product term clocks, output enables,
set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
• Programmable power reduction mode in each
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one
• Available in 84-pin PLCC, 100-pin PQFP, 100-pin
TQFP, and 160-pin PQFP packages
XC95108-15PQG100I Tags integrated circuit
1. Xilinx XC95108
2. XC95108 reference design
3. Xilinx In-System Programmable CPLD development board
4. XC95108-15PQG100I Datasheet PDF
5. In-System Programmable CPLD starter kit
6. In-System Programmable CPLD XC95108
7. XC95108 development board
8. In-System Programmable CPLD evaluation kit
9. XC95108-15PQG100I Datasheet PDF
Xilinx XC95108-15PQG100I TechnicalAttributes