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XC95288XV-7TQ144C FAQ Chips
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ICs XC95288XV-7TQ144C Features
20 year data retention
Optimized for high-performance 2.5V systems
280-pin CSP (192 user I/O pins)
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Local clock inversion with three global and one product-term clocks
Individual output enable per output pin
Superior pin-locking and routability with Fast CONNECT II switch matrix
ESD protection exceeding 2,000V
144-pin TQFP (117 user I/O pins)
288 macrocells with 6,400 usable gates
208-pin PQFP (168 user I/O pins)
Bus-hold ciruitry on all user pin inputs
Fast concurrent programming
Slew rate control on individual outputs
Four separate output banks
Extra wide 54-input Function Blocks
Enhanced data security features
Available in small footprint packages
256-pin FBGA (192 user I/O pins)
Low power operation
Advanced system features
Up to 90 product-terms per macrocell with individual product-term allocation
Excellent quality and reliability
Input hysteresis on all user and boundary-scan pin inputs
Request XC95288XV-7TQ144C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XC95288XV-7TQ144C Overview
The XC95288XV-7TQ144C is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns.Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* fwhere:MCHS = # macrocells in high-speed configurationPTHS = average number of high-speed product terms per macrocellMCLP = # macrocells in low power configurationPTLP = average number of low power product terms per macrocellf = maximum clock frequencyMCTOG = average % of flip-flops toggling per clock (~12%)This calculation was derived from laboratory measurements of an XC9500XL part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation.
The Xilinx Programmable logic array series XC95288XV-7TQ144C is High-Performance CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC95288XV-7TQ144C Tags integrated circuit
1. XC95288 development board
2. XC95288 evaluation board
3. High-Performance CPLD starter kit
4. High-Performance CPLD XC95288
5. XC95288 reference design
6. High-Performance CPLD evaluation kit
7. Xilinx High-Performance CPLD development board
8. Xilinx XC95288
9. High-Performance CPLD XC95288
Xilinx XC95288XV-7TQ144C TechnicalAttributes
-Supplier Device Package 144-TQFP (20×20)
-Delay Time tpd(1) Max 7.5ns
-Number of I/O 117
-Programmable Type In System Programmable
-Number of Logic Elements/Blocks 16
-Number of Macrocells 288
-Operating Temperature 0℃ ~ 70℃ (TA)
-Mounting Type Surface Mount
-Number of Gates 6400
-Package / Case 144-LQFP
-Voltage Supply – Internal 2.37V ~ 2.62V