XC9572-10PCG84C ApplicationField
-Consumer Electronics
-Artificial Intelligence
-Industrial Control
-Cloud Computing
-5G Technology
-Medical Equipment
-Wireless Technology
-Internet of Things
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XC9572-10PCG84C FAQ Chips
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Q: How to obtain XC9572-10PCG84C technical support documents?
A: Enter the “XC9572-10PCG84C” keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: How can I obtain software development tools related to the Xilinx FPGA platform?
A: In FPGA/CPLD design tools, Xilinx’s Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
ICs XC9572-10PCG84C Features
Available in small footprint packages
ESD protection exceeding 2,000V
Individual output enable per output pin
100-pin TQFP (72-user I/O pins)
Optimized for high-performance 2.5V systems
Superior pin-locking and routability with Fast CONNECT II switch matrix
In-system programmable
Slew rate control on individual outputs
Local clock inversion with three global and one product-term clocks
Fast concurrent programming
Enhanced data security features
Input hysteresis on all user and boundary-scan pin inputs
Up to 90 product-terms per macrocell with individual product-term allocation
72 macrocells with 1,600 usable gates
Advanced system features
Excellent quality and reliability
20 year data retention
Extra wide 54-input Function Blocks
Bus-hold ciruitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Multi-voltage operation
Low power operation
44-pin VQFP (34 user I/O pins)
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Xilinx XC9572-10PCG84C Overview
Description
The XC9572-10PCG84C is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
Features
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5V in-system programmable
– Endurance of 10,000 program/erase cycles
– Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
– 90 product terms drive any or all of 18 macrocells
within Function Block
– Global and product term clocks, output enables,
set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design
protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP,
and 100-pin TQFP package
XC9572-10PCG84C Tags integrated circuit
1. High-performance CPLD evaluation kit
2. XC9572 evaluation board
3. XC9572 reference design
4. Xilinx XC9572
5. XC9572-10PCG84C Datasheet PDF
6. High-performance CPLD starter kit
7. XC9572 development board
8. Xilinx High-performance CPLD development board
9. Xilinx XC9572
Xilinx XC9572-10PCG84C TechnicalAttributes
-Voltage Supply – Internal 4.75V ~ 5.25V
-Number of Gates 1600
-Delay Time tpd(1) Max 10.0ns
-Number of Logic Elements/Blocks 4
-Operating Temperature 0℃ ~ 70℃ (TA)
-Mounting Type Surface Mount
-Supplier Device Package 84-PLCC (29.31×29.31)
-Programmable Type In System Programmable (min 10K program/erase cycles)
-Package / Case 84-LCC (J-Lead)
-Number of Macrocells 72
-Number of I/O 69
