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XC9572-10PQG100C FAQ Chips
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ICs XC9572-10PQG100C Features
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Xilinx XC9572-10PQG100C Overview
The XC9572-10PQG100C is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns.
Power dissipation can be reduced in the XC9572-10PQG100C by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5V in-system programmable
– Endurance of 10,000 program/erase cycles
– Program/erase over full commercial voltage and temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
– 90 product terms drive any or all of 18 macrocells within Function Block
– Global and product term clocks, output enables, set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
• Programmable power reduction mode in each macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one XC9500 concurrently
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages
XC9572-10PQG100C Tags integrated circuit
1. Xilinx High-performance CPLD development board
2. Xilinx XC9572
3. High-performance CPLD XC9572
4. XC9572 reference design
5. XC9572 evaluation board
6. High-performance CPLD starter kit
7. XC9572-10PQG100C Datasheet PDF
8. XC9572 development board
9. XC9572 reference design
Xilinx XC9572-10PQG100C TechnicalAttributes