XCR3064XL-10VQG44C ApplicationField
-Internet of Things
-Consumer Electronics
-Artificial Intelligence
-Wireless Technology
-Medical Equipment
-5G Technology
-Industrial Control
-Cloud Computing
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XCR3064XL-10VQG44C FAQ Chips
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ICs XCR3064XL-10VQG44C Features
56-ball CP BGA (48 user I/O pins)
5.5 ns pin-to-pin logic delays
100-pin VQFP (68 user I/O pins)
Low power 3.3V 64 macrocell CPLD
Four global clocks
Up to 23 available clocks per function block
64 macrocells with 1,500 usable gates
48-ball CS BGA (40 user I/O pins)
Security bit prevents unauthorized access
Excellent pin retention during design changes
Available in small footprint packages44-pin VQFP (36 user I/O pins)48-ball CS BGA (40 user I/O pins)56-ball CP BGA (48 user I/O pins)100-pin VQFP (68 user I/O pins)
Advanced system featuresIn-system programmingInput registersPredictable timing modelUp to 23 available clocks per function blockExcellent pin retention during design changesFull IEEE Standard 1149.1 boundary-scan (JTAG)Four global clocksEight product term control terms per function block
Eight product term control terms per function block
5V tolerant I/O pins with 3.3V core supply
Typical Standby Current of 17 μA at 25°C
2.7V to 3.6V supply voltage at industrial temperature range
Ultra-low power operation
Optimized for 3.3V systemsUltra-low power operationTypical Standby Current of 17 μA at 25°C5V tolerant I/O pins with 3.3V core supplyAdvanced 0.35 micron five layer metal EEPROM processFast Zero Power CMOS design technology3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance)
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Input registers
44-pin VQFP (36 user I/O pins)
Fast Zero Power CMOS design technology
System frequencies up to 192 MHz
Fast ISP programming times
Programmable slew rate control per macrocell
Refer to XPLA3 family data sheet (DS012) for architecture description
Predictable timing model
In-system programming
3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance)
Port Enable pin for dual function of JTAG ISP pins
Advanced 0.35 micron five layer metal EEPROM process
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Xilinx XCR3064XL-10VQG44C Overview
The CoolRunner™ XPLA3 XCR3064XL-10VQG44C device is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are as fast as 5.5 ns with a maximum system frequency of 192 MHz.
The Xilinx Embedded – CPLDs (Complex Programmable Logic Devices) series XCR3064XL-10VQG44C is CPLD CoolRunner XPLA3 Family 1.5K Gates 64 Macro Cells 95MHz 0.35um (CMOS) Technology 3.3V , View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XCR3064XL-10VQG44C Tags integrated circuit
1. Xilinx Macrocell CPLD development board
2. Macrocell CPLD XCR3064XL
3. XCR3064XL development board
4. Macrocell CPLD evaluation kit
5. XCR3064XL reference design
6. XCR3064XL evaluation board
7. XCR3064XL-10VQG44C Datasheet PDF
8. Macrocell CPLD starter kit
9. Macrocell CPLD evaluation kit
Xilinx XCR3064XL-10VQG44C TechnicalAttributes
-Programmable Type In System Programmable (min 1K program/erase cycles)
-Number of Macrocells 64
-Package / Case 44-TQFP
-Supplier Device Package 44-VQFP (10×10)
-Mounting Type Surface Mount
-Delay Time tpd(1) Max 9.1ns
-Voltage Supply – Internal 3V ~ 3.6V
-Operating Temperature 0℃ ~ 70℃ (TA)
-Number of I/O 36
-Number of Gates 1500
-Number of Logic Elements/Blocks 4
