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XCR3064XL-7VQG44C FAQ Chips
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ICs XCR3064XL-7VQG44C Features
Refer to XPLA3 family data sheet (DS012) for architecture description
Fast Zero Power CMOS design technology
3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance)
Advanced system featuresIn-system programmingInput registersPredictable timing modelUp to 23 available clocks per function blockExcellent pin retention during design changesFull IEEE Standard 1149.1 boundary-scan (JTAG)Four global clocksEight product term control terms per function block
Programmable slew rate control per macrocell
Fast ISP programming times
48-ball CS BGA (40 user I/O pins)
System frequencies up to 192 MHz
Low power 3.3V 64 macrocell CPLD
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM process
64 macrocells with 1,500 usable gates
Excellent pin retention during design changes
Predictable timing model
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Up to 23 available clocks per function block
Optimized for 3.3V systemsUltra-low power operationTypical Standby Current of 17 μA at 25°C5V tolerant I/O pins with 3.3V core supplyAdvanced 0.35 micron five layer metal EEPROM processFast Zero Power CMOS design technology3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance)
Available in small footprint packages44-pin VQFP (36 user I/O pins)48-ball CS BGA (40 user I/O pins)56-ball CP BGA (48 user I/O pins)100-pin VQFP (68 user I/O pins)
2.7V to 3.6V supply voltage at industrial temperature range
Port Enable pin for dual function of JTAG ISP pins
56-ball CP BGA (48 user I/O pins)
5.5 ns pin-to-pin logic delays
Security bit prevents unauthorized access
44-pin VQFP (36 user I/O pins)
Four global clocks
Eight product term control terms per function block
Typical Standby Current of 17 μA at 25°C
100-pin VQFP (68 user I/O pins)
Ultra-low power operation
Request XCR3064XL-7VQG44C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XCR3064XL-7VQG44C Overview
The CoolRunner™ XPLA3 XCR3064XL-7VQG44C device is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are as fast as 5.5 ns with a maximum system frequency of 192 MHz.
The Xilinx CPLDs series XCR3064XL-7VQG44C is CPLD CoolRunner XPLA3 Family 1.5K Gates 64 Macro Cells 119MHz 0.35um (CMOS) Technology 3.3V 44Pin VTQFP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XCR3064XL-7VQG44C Tags integrated circuit
1. XCR3064XL development board
2. Macrocell CPLD evaluation kit
3. Macrocell CPLD XCR3064XL
4. Macrocell CPLD starter kit
5. Xilinx XCR3064XL
6. XCR3064XL evaluation board
7. XCR3064XL-7VQG44C Datasheet PDF
8. XCR3064XL reference design
9. Macrocell CPLD starter kit
Xilinx XCR3064XL-7VQG44C TechnicalAttributes
-Number of Macrocells 64
-Voltage Supply – Internal 3V ~ 3.6V
-Operating Temperature 0℃ ~ 70℃ (TA)
-Supplier Device Package 44-VQFP (10×10)
-Programmable Type In System Programmable (min 1K program/erase cycles)
-Number of I/O 36
-Number of Gates 1500
-Delay Time tpd(1) Max 7.0ns
-Mounting Type Surface Mount
-Package / Case 44-TQFP
-Number of Logic Elements/Blocks 4