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XCR3128XL-6TQG144C FAQ Chips
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ICs XCR3128XL-6TQG144C Features
Four output enable controls per function block
Four global clocks and one universal control term clock per device
Support for complex asynchronous clocking
Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade
3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface
Universal 3-state which facilitates “bed of nails” testing
Design entry/verification using Xilinx or industry standard CAE tools
Fast Zero Power (FZP) design technique provides ultra-low power and very high speed
Fast programming times
Typical Standby Current of 17 to 18 μA at 25°C
Excellent pin retention during design changes
Innovative CoolRunner XPLA3 architecture combines high speed with extreme flexibility
16 product term clocks and four local control term clocks per function block
Security bit prevents unauthorized access
Based on industry`s first TotalCMOS PLD — both CMOS design and process technologies
Advanced 0.35μ five layer metal EEPROM process
Available in Chip-scale BGA, Fineline BGA, and QFP packages. Pb-free available for most package types. See Xilinx Packaging for more information.
Supports hot-plugging capability
5V tolerant I/O pins
Foldback NAND for synthesis optimization
Full Boundary-Scan Test (IEEE 1149.1)
Request XCR3128XL-6TQG144C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XCR3128XL-6TQG144C Overview
The XCR3128XL-6TQG144C is targeted for low power systems that include portable, handheld, and power sensitive applications.，includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the XCR3128XL-6TQG144C offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for “turbo bits” or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. XCR3128XL-6TQG144C devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.CoolRunner XPLA3 CPLDs are supported by Xilinx WebPACK software and industry standard CAE tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog, and/or schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on multiple personal computer (PC), Sun, and HP platforms.The XCR3128XL-6TQG144C is electrically reprogrammable using industry standard device programmers.
The Xilinx CPLDs series XCR3128XL-6TQG144C is CPLD CoolRunner XPLA3 Family 3K Gates 128 Macro Cells 175MHz 0.35um (CMOS) Technology 3.3V 144Pin TQFP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XCR3128XL-6TQG144C Tags integrated circuit
1. Macrocell CPLD starter kit
2. Macrocell CPLD evaluation kit
3. XCR3128XL development board
4. Xilinx Macrocell CPLD development board
5. XCR3128XL reference design
6. Xilinx XCR3128XL
7. XCR3128XL evaluation board
8. Macrocell CPLD XCR3128XL
9. Xilinx Macrocell CPLD development board
Xilinx XCR3128XL-6TQG144C TechnicalAttributes
-Number of I/O 108
-Delay Time tpd(1) Max 5.5ns
-Mounting Type Surface Mount
-Number of Macrocells 128
-Programmable Type In System Programmable (min 1K program/erase cycles)
-Number of Gates 3000
-Package / Case 144-LQFP
-Voltage Supply – Internal 3V ~ 3.6V
-Number of Logic Elements/Blocks 8
-Supplier Device Package 144-TQFP (20×20)
-Operating Temperature 0℃ ~ 70℃ (TA)