XCR3384XL-10PQG208I ApplicationField
-Cloud Computing
-Medical Equipment
-5G Technology
-Internet of Things
-Artificial Intelligence
-Industrial Control
-Consumer Electronics
-Wireless Technology
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XCR3384XL-10PQG208I FAQ Chips
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ICs XCR3384XL-10PQG208I Features
Excellent pin retention during design changes
High-speed pin-to-pin delays of 5.0 ns
Slew rate control per output
Typical Standby Current of 17 to 18 μA at 25°C
Fast Zero Power (FZP) design technique provides ultra-low power and very high speed
Foldback NAND for synthesis optimization
Innovative CoolRunner XPLA3 architecture combines high speed with extreme flexibility
Universal 3-state which facilitates “bed of nails” testing
Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade
Based on industry`s first TotalCMOS PLD — both CMOS design and process technologies
Single pass logic expandable to 48 product terms
Design entry/verification using Xilinx or industry standard CAE tools
Support for complex asynchronous clocking
3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface
Four global clocks and one universal control term clock per device
Advanced 0.35μ five layer metal EEPROM process
Supports hot-plugging capability
Security bit prevents unauthorized access
100% routable
Input register setup time of 2.5 ns
5V tolerant I/O pins
Available in Chip-scale BGA, Fineline BGA, and QFP packages. Pb-free available for most package types. See Xilinx Packaging for more information.
16 product term clocks and four local control term clocks per function block
Four output enable controls per function block
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Xilinx XCR3384XL-10PQG208I Overview
The XCR3384XL-10PQG208I is targeted for low power systems that include portable, handheld, and power sensitive applications.,includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the XCR3384XL-10PQG208I offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for “turbo bits” or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. XCR3384XL-10PQG208I devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.CoolRunner XPLA3 CPLDs are supported by Xilinx WebPACK software and industry standard CAE tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog, and/or schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on multiple personal computer (PC), Sun, and HP platforms.The XCR3384XL-10PQG208I is electrically reprogrammable using industry standard device programmers.
The Xilinx CPLDs series XCR3384XL-10PQG208I is CPLD CoolRunner XPLA3 Family 9K Gates 384 Macro Cells 102MHz 0.35um (CMOS) Technology 3.3, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XCR3384XL-10PQG208I Tags integrated circuit
1. Xilinx XCR3384XL
2. Macrocell CPLD XCR3384XL
3. Macrocell CPLD evaluation kit
4. XCR3384XL-10PQG208I Datasheet PDF
5. XCR3384XL reference design
6. XCR3384XL development board
7. XCR3384XL evaluation board
8. Xilinx Macrocell CPLD development board
9. XCR3384XL-10PQG208I Datasheet PDF
Xilinx XCR3384XL-10PQG208I TechnicalAttributes
-Supplier Device Package 208-PQFP (28×28)
-Number of Macrocells 384
-Number of I/O 172
-Operating Temperature -40℃ ~ 85℃ (TA)
-Delay Time tpd(1) Max 9.0ns
-Number of Gates 9000
-Voltage Supply – Internal 2.7V ~ 3.6V
-Package / Case 208-BFQFP
-Programmable Type In System Programmable (min 1K program/erase cycles)
-Mounting Type Surface Mount
-Number of Logic Elements/Blocks 24