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XCR3512XL-10FG324I FAQ Chips
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ICs XCR3512XL-10FG324I Features
Innovative CoolRunner XPLA3 architecture combines high speed with extreme flexibility
20 years data retention guaranteed
Available in Chip-scale BGA, Fineline BGA, and QFP packages. Pb-free available for most package types. See Xilinx Packaging for more information.
Full Boundary-Scan Test (IEEE 1149.1)
Typical Standby Current of 17 to 18 μA at 25°C
1,000 erase/program cycles guaranteed
Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade
Based on industry`s first TotalCMOS PLD — both CMOS design and process technologies
Advanced 0.35μ five layer metal EEPROM process
Support for complex asynchronous clocking
Universal 3-state which facilitates “bed of nails” testing
16 product term clocks and four local control term clocks per function block
Four output enable controls per function block
Fast Zero Power (FZP) design technique provides ultra-low power and very high speed
3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface
Excellent pin retention during design changes
Four global clocks and one universal control term clock per device
Foldback NAND for synthesis optimization
5V tolerant I/O pins
Fast programming times
Request XCR3512XL-10FG324I FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XCR3512XL-10FG324I Overview
The XCR3512XL-10FG324I is targeted for low power systems that include portable, handheld, and power sensitive applications.，includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the XCR3512XL-10FG324I offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for “turbo bits” or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. XCR3512XL-10FG324I devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.CoolRunner XPLA3 CPLDs are supported by Xilinx WebPACK software and industry standard CAE tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog, and/or schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on multiple personal computer (PC), Sun, and HP platforms.The XCR3512XL-10FG324I is electrically reprogrammable using industry standard device programmers.
The Xilinx Programmable logic array series XCR3512XL-10FG324I is XCR3512XL: 512 Macrocell CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XCR3512XL-10FG324I Tags integrated circuit
1. Macrocell CPLD starter kit
2. Xilinx Macrocell CPLD development board
3. Macrocell CPLD evaluation kit
4. XCR3512XL development board
5. XCR3512XL-10FG324I Datasheet PDF
6. Xilinx XCR3512XL
7. XCR3512XL reference design
8. Macrocell CPLD XCR3512XL
9. XCR3512XL development board
Xilinx XCR3512XL-10FG324I TechnicalAttributes
-Number of I/O 260
-Mounting Type Surface Mount
-Supplier Device Package 324-FBGA (23×23)
-Number of Gates 12000
-Programmable Type In System Programmable (min 1K program/erase cycles)
-Number of Logic Elements/Blocks 32
-Package / Case 324-BBGA
-Operating Temperature -40℃ ~ 85℃ (TA)
-Number of Macrocells 512
-Voltage Supply – Internal 2.7V ~ 3.6V
-Delay Time tpd(1) Max 9.0ns