XCR3512XL-10FTG256I ApplicationField
-Industrial Control
-Medical Equipment
-Internet of Things
-Wireless Technology
-Consumer Electronics
-Cloud Computing
-5G Technology
-Artificial Intelligence
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XCR3512XL-10FTG256I FAQ Chips
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ICs XCR3512XL-10FTG256I Features
Support for complex asynchronous clocking
16 product term clocks and four local control term clocks per function block
1,000 erase/program cycles guaranteed
Typical Standby Current of 17 to 18 μA at 25°C
Four output enable controls per function block
Advanced 0.35μ five layer metal EEPROM process
Four global clocks and one universal control term clock per device
20 years data retention guaranteed
Fast Zero Power (FZP) design technique provides ultra-low power and very high speed
Full Boundary-Scan Test (IEEE 1149.1)
Foldback NAND for synthesis optimization
Based on industry`s first TotalCMOS PLD — both CMOS design and process technologies
Available in Chip-scale BGA, Fineline BGA, and QFP packages. Pb-free available for most package types. See Xilinx Packaging for more information.
Universal 3-state which facilitates “bed of nails” testing
Innovative CoolRunner XPLA3 architecture combines high speed with extreme flexibility
3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface
5V tolerant I/O pins
Fast programming times
Excellent pin retention during design changes
Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade
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Xilinx XCR3512XL-10FTG256I Overview
The XCR3512XL-10FTG256I is targeted for low power systems that include portable, handheld, and power sensitive applications.，includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the XCR3512XL-10FTG256I offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for “turbo bits” or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. XCR3512XL-10FTG256I devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.CoolRunner XPLA3 CPLDs are supported by Xilinx WebPACK software and industry standard CAE tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog, and/or schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on multiple personal computer (PC), Sun, and HP platforms.The XCR3512XL-10FTG256I is electrically reprogrammable using industry standard device programmers.
The Xilinx CPLDs series XCR3512XL-10FTG256I is CPLD CoolRunner XPLA3 Family 12K Gates 512 Macro Cells 97MHz 0.35um (CMOS) Technology 3.3V 256Pin FTBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XCR3512XL-10FTG256I Tags integrated circuit
1. XCR3512XL reference design
2. Xilinx XCR3512XL
3. Macrocell CPLD XCR3512XL
4. XCR3512XL development board
5. Xilinx Macrocell CPLD development board
6. XCR3512XL-10FTG256I Datasheet PDF
7. Macrocell CPLD starter kit
8. XCR3512XL evaluation board
9. XCR3512XL development board
Xilinx XCR3512XL-10FTG256I TechnicalAttributes
-Number of Logic Elements/Blocks 32
-Mounting Type Surface Mount
-Programmable Type In System Programmable (min 1K program/erase cycles)
-Delay Time tpd(1) Max 9.0ns
-Package / Case 256-LBGA
-Number of Gates 12000
-Number of I/O 212
-Supplier Device Package 256-FTBGA (17×17)
-Operating Temperature -40℃ ~ 85℃ (TA)
-Number of Macrocells 512
-Voltage Supply – Internal 2.7V ~ 3.6V
