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XCR3512XL-12PQ208I FAQ Chips
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ICs XCR3512XL-12PQ208I Features
Excellent pin retention during design changes
Available in Chip-scale BGA, Fineline BGA, and QFP packages. Pb-free available for most package types. See Xilinx Packaging for more information.
3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface
Advanced 0.35μ five layer metal EEPROM process
Innovative CoolRunner XPLA3 architecture combines high speed with extreme flexibility
Universal 3-state which facilitates “bed of nails” testing
Support for complex asynchronous clocking
Foldback NAND for synthesis optimization
5V tolerant I/O pins
Four global clocks and one universal control term clock per device
Four output enable controls per function block
20 years data retention guaranteed
Full Boundary-Scan Test (IEEE 1149.1)
1,000 erase/program cycles guaranteed
Fast programming times
Fast Zero Power (FZP) design technique provides ultra-low power and very high speed
16 product term clocks and four local control term clocks per function block
Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade
Typical Standby Current of 17 to 18 μA at 25°C
Based on industry`s first TotalCMOS PLD — both CMOS design and process technologies
Request XCR3512XL-12PQ208I FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XCR3512XL-12PQ208I Overview
The XCR3512XL-12PQ208I is targeted for low power systems that include portable, handheld, and power sensitive applications.，includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the XCR3512XL-12PQ208I offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for “turbo bits” or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. XCR3512XL-12PQ208I devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.CoolRunner XPLA3 CPLDs are supported by Xilinx WebPACK software and industry standard CAE tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog, and/or schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on multiple personal computer (PC), Sun, and HP platforms.The XCR3512XL-12PQ208I is electrically reprogrammable using industry standard device programmers.
The Xilinx Programmable logic array series XCR3512XL-12PQ208I is XCR3512XL: 512 Macrocell CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XCR3512XL-12PQ208I Tags integrated circuit
1. Macrocell CPLD XCR3512XL
2. Macrocell CPLD evaluation kit
3. Xilinx Macrocell CPLD development board
4. XCR3512XL development board
5. XCR3512XL reference design
6. Macrocell CPLD starter kit
7. XCR3512XL evaluation board
8. XCR3512XL-12PQ208I Datasheet PDF
9. XCR3512XL development board
Xilinx XCR3512XL-12PQ208I TechnicalAttributes
-Number of I/O 180
-Number of Logic Elements/Blocks 32
-Mounting Type Surface Mount
-Number of Gates 12000
-Operating Temperature -40℃ ~ 85℃ (TA)
-Voltage Supply – Internal 2.7V ~ 3.6V
-Supplier Device Package 208-PQFP (28×28)
-Package / Case 208-BFQFP
-Number of Macrocells 512
-Programmable Type In System Programmable (min 1K program/erase cycles)
-Delay Time tpd(1) Max 10.8ns