EP1M120F484C5N ApplicationField
-Cloud Computing
-Internet of Things
-Medical Equipment
-Industrial Control
-Consumer Electronics
-Wireless Technology
-Artificial Intelligence
-5G Technology
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ICs EP1M120F484C5N Features
System-level features
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Xilinx EP1M120F484C5N Overview
Mercury EP1M120F484C5N devices integrate high-speed differential transceivers and support for CDR with a speed-optimized PLD architecture. These transceivers are implemented through the dedicated serializer, deserializer, and clock recovery circuitry in the HSDI and incorporate support for the LVDS, LVPECL, and 3.3-V PCML I/O standards. This circuitry, together with enhanced I/O elements (IOEs) and support for numerous I/O standards, allows Mercury devices to meet high-speed interface requirements.Mercury EP1M120F484C5N are the first PLDs optimized for core performance. These LUT-based, enhanced memory devices use a network of fast routing resources to achieve optimal performance. These resources are ideal for data-path, register-intensive, mathematical, digital signal processing (DSP), or communications designs.
The INTEL FPGA – Field Programmable Gate Array series EP1M120F484C5N is FPGA – Field Programmable Gate Array FPGA – MERCURY 480 LABs 303 IOs, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
EP1M120F484C5N Tags integrated circuit
1. Mercury PLD EP1M120
2. EP1M120F484C5N Datasheet PDF
3. INTEL EP1M120
4. EP1M120 reference design
5. Mercury PLD evaluation kit
6. EP1M120 development board
7. EP1M120 evaluation board
8. Mercury PLD starter kit
9. EP1M120 reference design
Xilinx EP1M120F484C5N TechnicalAttributes
-Number of I/Os 303
-Operating Supply Current 30 mA
-Operating Supply Voltage 3.3 V
-Distributed RAM 49 kbit
-Maximum Operating Temperature + 85℃
-Package / Case FBGA-484
-Series Mercury
-Minimum Operating Temperature – 40℃
-Packaging Tray
-Number of Logic Blocks 480
-Mounting Style SMD/SMT