EP20K60EFC324-1 ApplicationField
-Artificial Intelligence
-Wireless Technology
-Consumer Electronics
-Cloud Computing
-5G Technology
-Internet of Things
-Industrial Control
-Medical Equipment
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ICs EP20K60EFC324-1 Features
■ Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
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Xilinx EP20K60EFC324-1 Overview
Features
■ Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
– MultiCoreTM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
– LUT logic used for register-intensive functions
– Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
– ESB implementation of product-term logic used for
combinatorial-intensive functions
■ High density
– 30,000 to 1.5 million typical gates (see Tables 1 and 2)
– Up to 51,840 logic elements (LEs)
– Up to 442,368 RAM bits that can be used without reducing
available logic
– Up to 3,456 product-term-based macrocells
■ Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
– Built-in low-skew clock tree
– Up to eight global clock signals
– ClockLock® feature reducing clock delay and skew
– ClockBoost® feature providing clock multiplication and division
– ClockShiftTM programmable clock phase and delay shifting
■ Powerful I/O features
– Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
– Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
– Bidirectional I/O performance (tCO + tSU) up to 250 MHz
– LVDS performance up to 840 Mbits per channel
– Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
– MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
– Programmable clamp to VCCIO
– Individual tri-state output enable control for each pin
– Programmable output slew-rate control to reduce switching
noise
– Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stubseries
terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
– Pull-up on I/O pins before and during configuration
■ Advanced interconnect structure
– Four-level hierarchical FastTrack® Interconnect structure
providing fast, predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
– Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
– Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
■ Advanced packaging options
– Available in a variety of packages with 144 to 1,020 pins (see
Tables 4 through 7)
– FineLine BGA® packages maximize board space efficiency
■ Advanced software support
– Software design support and automatic place-and-route
provided by the Altera® Quartus® II development system for
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
– Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
– NativeLinkTM integration with popular synthesis, simulation,
and timing analysis tools
– Quartus II SignalTap® embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
– Supports popular revision-control software packages including
PVCS, Revision Control System (RCS), and Source Code Control
System (SCCS )
General
Description
APEXTM 20K devices are the first PLDs designed with the MultiCore
architecture, which combines the strengths of LUT-based and productterm-based
devices with an enhanced memory structure.
LUT-based logic
provides optimized performance and efficiency for data-path, registerintensive,
mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths,
such as complex state machines.
LUT- and product-term-based logic
combined with memory functions and a wide variety of MegaCore and
AMPP functions make the APEX 20K device architecture uniquely suited
for system-on-a-programmable-chip designs.
Applications historically
requiring a combination of LUT-, product-term-, and memory-based
devices can now be integrated into one APEX 20K device.
APEX 20KE devices are a superset of APEX 20K devices and include
additional features such as advanced I/O standard support, CAM,
additional global clocks, and enhanced ClockLock clock circuitry.
In
addition, APEX 20KE devices extend the APEX 20K family to 1.5 million
gates.
APEX 20KE devices are denoted with an “E” suffix in the device
name (e.g., the EP20K1000E device is an APEX 20KE device).
Table 8
compares the features included in APEX 20K and APEX 20KE devices.
The INTEL FPGA – Field Programmable Gate Array series EP20K60EFC324-1 is FPGA – Field Programmable Gate Array CPLD – APEX 20K 256 Macro 196 IOs, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
EP20K60EFC324-1 Tags integrated circuit
1. APEX 20KE EP20K60E
2. APEX 20KE starter kit
3. EP20K60E evaluation board
4. EP20K60E development board
5. EP20K60EFC324-1 Datasheet PDF
6. INTEL APEX 20KE development board
7. EP20K60E reference design
8. INTEL EP20K60E
9. EP20K60E development board
Xilinx EP20K60EFC324-1 TechnicalAttributes
-Minimum Operating Temperature 0 C
-Packaging Tray
-Series APEX 20K
-Maximum Operating Frequency 180 MHz
-Package / Case FBGA-324
-Maximum Operating Temperature + 70 C
-Mounting Style SMD/SMT
-Operating Supply Voltage 1.8 V
