EPM7256EGC192-12EM ApplicationField
-5G Technology
-Artificial Intelligence
-Industrial Control
-Cloud Computing
-Internet of Things
-Wireless Technology
-Medical Equipment
-Consumer Electronics
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ICs EPM7256EGC192-12EM Features
– ISP circuitry compatible with IEEE Std. 1532
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX architecture
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
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Xilinx EPM7256EGC192-12EM Overview
Features
■ High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX®architecture
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
■ PCI-compliant devices available
■ Open-drain output option in MAX 7000S devices
■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
■ Programmable power-saving mode for a reduction of over 50% in each macrocell
■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
■ Programmable security bit for protection of proprietary designs
■ 3.3-V or 5.0-V operation
– MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
– Pin compatible with low-voltage MAX 7000A and MAX 7000B devices
■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest
■ Programming support
– Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices
– The BitBlaster TM serial download cable, ByteBlasterMV TM parallel port download cable, and MasterBlaster TM serial/universal serial bus (USB) download cable program MAX 7000S devices
Description
The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.
The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256EGC192-12EM devices—have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.
In-system programmable MAX 7000 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option.
The MAX 7000 architecture includes the following elements:
■ Logic array blocks
■ Macrocells
■ Expander product terms (shareable and parallel)
■ Programmable interconnect array
■ I/O control blocks
EPM7256EGC192-12EM Tags integrated circuit
1. EPM7256E evaluation board
2. MAX 7000 evaluation kit
3. Altera EPM7256E
4. MAX 7000 EPM7256E
5. EPM7256E development board
6. Altera MAX 7000 development board
7. MAX 7000 starter kit
8. EPM7256E reference design
9. MAX 7000 EPM7256E
Xilinx EPM7256EGC192-12EM TechnicalAttributes
-Maximum Operating Frequency 90.9 MHz
-Number of Programmable I/Os 164
-Mounting Style SMD/SMT
-Number of Macrocells 256
-Minimum Operating Temperature 0 C
-Package / Case PGA-192
-Series MAX 7000
-Memory Type EEPROM
-Supply Voltage – Max 5.25 V
-Packaging Tray
-Delay Time 12 ns
-Operating Supply Voltage 5 V
-Supply Voltage – Min 4.75 V
-Maximum Operating Temperature + 70 C
