EPM9480RC208-15N ApplicationField
-Cloud Computing
-Artificial Intelligence
-5G Technology
-Consumer Electronics
-Wireless Technology
-Medical Equipment
-Industrial Control
-Internet of Things
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EPM9480RC208-15N FAQ Chips
Q: Where can I purchase Altera EPM9480 Development Boards, Evaluation Boards, or MAX 9000 EPLD Starter Kit? also provide technical information?
A: RAYPCB does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How can I obtain software development tools related to the Altera FPGA platform?
A: Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
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ICs EPM9480RC208-15N Features
■ Fully compliant with the peripheral component interconnect Special Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
■ High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1)
■ FastTrack Interconnect for fast, predictable interconnect delays
■ Programmable output slew-rate control to reduce switching noise
■ Configurable expander product-term distribution allowing up to 32 product terms per macrocell
■ Dual-output macrocell for independent use of combinatorial and registered logic
High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX) architecture
■ 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz
■ Input/output registers with clear and clock enable on all I/O pins
■ Programmable power-saving mode for more than 50% power reduction in each macrocell
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface
■ MultiVolt I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices
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Xilinx EPM9480RC208-15N Overview
The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.
EPM9480RC208-15N Tags integrated circuit
1. EPM9480 reference design
2. EPM9480RC208-15N Datasheet PDF
3. Altera EPM9480
4. EPM9480 evaluation board
5. Altera MAX 9000 Devices development board
6. EPM9480 development board
7. MAX 9000 Devices EPM9480
8. MAX 9000 Devices evaluation kit
9. EPM9480 evaluation board
Xilinx EPM9480RC208-15N TechnicalAttributes
-Voltage Supply – Internal 4.75V ~ 5.25V
-Number of I/O 175
-Mounting Type Surface Mount
-Delay Time tpd(1) Max 20.0ns
-Operating Temperature 0??C ~ 70??C (TA)
-Programmable Type In System Programmable
-Number of Logic Elements/Blocks 30
-Number of Macrocells 480
-Supplier Device Package 240-RQFP (32×32)
-Number of Gates 10000
-Package / Case 240-BFQFP Exposed Pad
