EPM9560ARC208-10N ApplicationField
-Wireless Technology
-Artificial Intelligence
-Industrial Control
-Internet of Things
-Consumer Electronics
-Medical Equipment
-Cloud Computing
-5G Technology
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EPM9560ARC208-10N FAQ Chips
Q: How can I obtain software development tools related to the INTEL FPGA platform?
A: Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
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Q: Where can I purchase INTEL EPM9560A Development Boards, Evaluation Boards, or MAX 9000 EPLD Starter Kit? also provide technical information?
A: RAYPCB does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
ICs EPM9560ARC208-10N Features
■ Programmable output slew-rate control to reduce switching noise
devices (PLDs) built on third-generation Multiple Array MatriX
■ Dual-output macrocell for independent use of combinatorial and
reduction in each macrocell
registered logic
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std.
■ High-density erasable programmable logic device (EPLD) family
■ MultiVolt I/O interface operation, allowing devices to interface with
■ FastTrack Interconnect for fast, predictable interconnect delays
■ Configurable expander product-term distribution allowing up to 32
■ Programmable power-saving mode for more than 50% power
(MAX) architecture
144 MHz
■ High-performance CMOS EEPROM-based programmable logic
■ Input/output registers with clear and clock enable on all I/O pins
■ Fully compliant with the peripheral component interconnect Special
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
ranging from 6,000 to 12,000 usable gates (see Table 1)
3.3-V and 5.0-V devices
■ 10-ns pin-to-pin logic delays with counter frequencies of up to
Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
Std. 1149.1-1990
1149.1 Joint Test Action Group (JTAG) interface
product terms per macrocell
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Xilinx EPM9560ARC208-10N Overview
The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX EPM9560ARC208-10N provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.
The INTEL CPLD – Complex Programmable Logic Devices series EPM9560ARC208-10N is MAX® 9000 Programmable Logic Device (PLD) Family; 208 pin RQFP; 0 to 90°C, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
EPM9560ARC208-10N Tags integrated circuit
1. EPM9560A reference design
2. MAX 9000 Devices evaluation kit
3. EPM9560ARC208-10N Datasheet PDF
4. EPM9560A evaluation board
5. INTEL MAX 9000 Devices development board
6. MAX 9000 Devices EPM9560A
7. INTEL EPM9560A
8. EPM9560A development board
9. EPM9560A evaluation board
Xilinx EPM9560ARC208-10N TechnicalAttributes
-Series MAX 9000
-Number of Macrocells 560
-Supply Current 174 mA
-Maximum Operating Temperature + 70 C
-Minimum Operating Temperature 0 C
-Supply Voltage – Max 5.25 V
-Packaging Tray
-Package / Case QFP-208
-Supply Voltage – Min 4.75 V
-Delay Time 10 ns
-Number of Programmable I/Os 153
-Mounting Style SMD/SMT
-Maximum Operating Frequency 144 MHz
-Operating Supply Voltage 5 V
-Memory Type EEPROM
