EPM9560ARI208-10N ApplicationField
-Artificial Intelligence
-5G Technology
-Cloud Computing
-Industrial Control
-Medical Equipment
-Consumer Electronics
-Wireless Technology
-Internet of Things
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EPM9560ARI208-10N FAQ Chips
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Q: How can I obtain software development tools related to the Altera FPGA platform?
A: Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Altera EPM9560A Development Boards, Evaluation Boards, or MAX 9000 EPLD Starter Kit? also provide technical information?
A: RAYPCB does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
ICs EPM9560ARI208-10N Features
registered logic
Std. 1149.1-1990
■ MultiVolt I/O interface operation, allowing devices to interface with
reduction in each macrocell
■ FastTrack Interconnect for fast, predictable interconnect delays
■ Programmable power-saving mode for more than 50% power
■ Configurable expander product-term distribution allowing up to 32
product terms per macrocell
■ Programmable output slew-rate control to reduce switching noise
■ Dual-output macrocell for independent use of combinatorial and
Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
■ Fully compliant with the peripheral component interconnect Special
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std.
(MAX) architecture
3.3-V and 5.0-V devices
1149.1 Joint Test Action Group (JTAG) interface
devices (PLDs) built on third-generation Multiple Array MatriX
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
■ 10-ns pin-to-pin logic delays with counter frequencies of up to
■ High-density erasable programmable logic device (EPLD) family
ranging from 6,000 to 12,000 usable gates (see Table 1)
144 MHz
■ High-performance CMOS EEPROM-based programmable logic
■ Input/output registers with clear and clock enable on all I/O pins
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Xilinx EPM9560ARI208-10N Overview
The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX EPM9560ARI208-10N provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.
EPM9560ARI208-10N Tags integrated circuit
1. Altera EPM9560A
2. EPM9560A evaluation board
3. EPM9560A development board
4. MAX 9000 Devices starter kit
5. MAX 9000 Devices evaluation kit
6. EPM9560ARI208-10N Datasheet PDF
7. EPM9560A reference design
8. MAX 9000 Devices EPM9560A
9. MAX 9000 Devices starter kit
Xilinx EPM9560ARI208-10N TechnicalAttributes
-Packaging Tray
-Supply Voltage – Max 5.25 V
-Series MAX 9000
-Package / Case QFP-240
-Mounting Style SMD/SMT
-Maximum Operating Temperature + 85 C
-Delay Time 10 ns
-Minimum Operating Temperature – 40 C
-Maximum Operating Frequency 144 MHz
-Memory Type EEPROM
-Number of Macrocells 560
-Operating Supply Voltage 5 V
-Number of Programmable I/Os 191
-Supply Current 174 mA
-Supply Voltage – Min 4.75 V
